FIFOsareoftenusedtosafelypassdatafromoneclockdomaintoanotherasynchronousclockdomain.UsingaFIFOtopassdatafromoneclockdomaintoanotherclockdomainrequiresmulti-asynchronousclockdesigntechniques.TherearemanywaystodesignaFIFOwrong.TherearemanywaystodesignaFIFOrightbutstillmakeitdifficulttoproperlysynthesizeandanalyzethedesign.Thispaperwilldetailonemethodthatisusedtodesign,synthesizeandanalyzeasafeFIFObetweendifferentclockdomainsusingGraycodepointersthataresynchronizedintoadifferentclockdomainbeforetestingfor"FIFOfull"or"FIFOempty"conditions.Thefullycoded,synthesizedandanalyzedRTLVerilogmodel(FIFOStyle#1)isincluded.
1