FIFOsareoftenusedtosafelypassdatafromoneclockdomaintoanotherasynchronousclockdomain.UsingaFIFOtopassdatafromoneclockdomaintoanotherclockdomainrequiresmulti-asynchronousclockdesigntechniques.TherearemanywaystodesignaFIFOwrong.TherearemanywaystodesignaFIFOrightbutstillmakeitdifficulttoproperlysynthesizeandanalyzethedesign.Thispaperwilldetailonemethodthatisusedtodesign,synthesizeandanalyzeasafeFIFObetweendifferentclockdomainsusingGraycodepointersthataresynchronizedintoadifferentclockdomainbeforetestingfor"FIFOfull"or"FIFOempty"conditions.Thefullycoded,synthesizedandanalyzedRTLVerilogmodel(FIFOStyle#1)isincluded.
                                    
                                    
                                        
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