TheVerilog®HardwareDescriptionLanguage(VerilogHDL)becameanIEEEstandardin1995asIEEEStd1364-1995.Itwasdesignedtobesimple,intuitive,andeffectiveatmultiplelevelsofabstractioninastandardtextualformatforavarietyofdesigntools,includingverificationsimulation,timinganalysis,testanalysis,andsynthesis.ItisbecauseoftheserichfeaturesthatVeriloghasbeenacceptedtobethelanguageofchoicebyanoverwhelmingnumberofICdesigners.
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