UART实现Verilog版

[{"title":"（8个子文件10KB）UART实现Verilog版","children":[{"title":"irda_uart.v <span style='color:#111;'>1.32KB</span>","children":null,"spread":false},{"title":"sirendec.v <span style='color:#111;'>3.32KB</span>","children":null,"spread":false},{"title":"RXCVER.V <span style='color:#111;'>5.58KB</span>","children":null,"spread":false},{"title":"TXMIT.V <span style='color:#111;'>4.48KB</span>","children":null,"spread":false},{"title":"irda_uart_tb.v <span style='color:#111;'>2.19KB</span>","children":null,"spread":false},{"title":"Uart_tb.v <span style='color:#111;'>2.02KB</span>","children":null,"spread":false},{"title":"README.txt <span style='color:#111;'>6.50KB</span>","children":null,"spread":false},{"title":"UART.V <span style='color:#111;'>1.85KB</span>","children":null,"spread":false}],"spread":true}]