[{"title":"(18个子文件908KB)SVM分类器Verilog设计材料","children":[{"title":"SVM-Gaussian-Classification-FPGA-master","children":[{"title":"Readme.md <span style='color:#111;'>749B</span>","children":null,"spread":false},{"title":"VerilogCodes","children":[{"title":"tb.v <span style='color:#111;'>1.71KB</span>","children":null,"spread":false},{"title":"sub_table.v <span style='color:#111;'>16.16KB</span>","children":null,"spread":false},{"title":"ram_x.v <span style='color:#111;'>485B</span>","children":null,"spread":false},{"title":"ram_ai.v <span style='color:#111;'>471B</span>","children":null,"spread":false},{"title":"ram_z.v <span style='color:#111;'>474B</span>","children":null,"spread":false},{"title":"part_1.v <span style='color:#111;'>5.07KB</span>","children":null,"spread":false},{"title":"add_table.v <span style='color:#111;'>16.16KB</span>","children":null,"spread":false},{"title":"lookup_table.v <span style='color:#111;'>17.50KB</span>","children":null,"spread":false},{"title":"top_module.v <span style='color:#111;'>783B</span>","children":null,"spread":false},{"title":"part_2.v <span style='color:#111;'>3.44KB</span>","children":null,"spread":false},{"title":"lut_ai.v <span style='color:#111;'>3.45KB</span>","children":null,"spread":false},{"title":"adder_l1.v <span style='color:#111;'>463B</span>","children":null,"spread":false}],"spread":false},{"title":"Python_Code_Tester","children":[{"title":"init_x.dat <span style='color:#111;'>7.81KB</span>","children":null,"spread":false},{"title":"Hello <span style='color:#111;'>6B</span>","children":null,"spread":false},{"title":"init_a.dat <span style='color:#111;'>20.88KB</span>","children":null,"spread":false},{"title":"init_z.dat <span style='color:#111;'>4.59MB</span>","children":null,"spread":false},{"title":"python1.py <span style='color:#111;'>9.94KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]