FPGA完成以太网IP核

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style='color:#111;'>19.70KB</span>","children":null,"spread":false}],"spread":true},{"title":"bench","children":[{"title":"verilog","children":[{"title":"tb_ethernet_with_cop.v <span style='color:#111;'>20.05KB</span>","children":null,"spread":false},{"title":"tb_eth_defines.v <span style='color:#111;'>11.01KB</span>","children":null,"spread":false},{"title":"wb_master_behavioral.v <span style='color:#111;'>23.87KB</span>","children":null,"spread":false},{"title":"eth_memory.v <span style='color:#111;'>6.29KB</span>","children":null,"spread":false},{"title":"eth_host.v <span style='color:#111;'>5.09KB</span>","children":null,"spread":false},{"title":"wb_model_defines.v <span style='color:#111;'>7.51KB</span>","children":null,"spread":false},{"title":"wb_slave_behavioral.v <span style='color:#111;'>12.65KB</span>","children":null,"spread":false},{"title":"tb_ethernet.v <span style='color:#111;'>764.51KB</span>","children":null,"spread":false},{"title":"eth_phy_defines.v <span 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