[{"title":"(18个子文件349KB)基于FPGA的CPUVHDL设计","children":[{"title":"CPU_DESIGN_VHDL","children":[{"title":"report","children":[{"title":"Designreport.doc <span style='color:#111;'>827.00KB</span>","children":null,"spread":false}],"spread":true},{"title":"cpu","children":[{"title":"jmpz.vhd <span style='color:#111;'>575B</span>","children":null,"spread":false},{"title":"mar.pof <span style='color:#111;'>512.18KB</span>","children":null,"spread":false},{"title":"pc.vhd <span style='color:#111;'>680B</span>","children":null,"spread":false},{"title":"ir.vhd <span style='color:#111;'>542B</span>","children":null,"spread":false},{"title":"mem.mif <span style='color:#111;'>1.44KB</span>","children":null,"spread":false},{"title":"mar.vhd <span style='color:#111;'>649B</span>","children":null,"spread":false},{"title":"sl_car.vhd <span style='color:#111;'>715B</span>","children":null,"spread":false},{"title":"acc.vhd <span style='color:#111;'>693B</span>","children":null,"spread":false},{"title":"mbr.vhd <span style='color:#111;'>757B</span>","children":null,"spread":false},{"title":"sl.vhd <span style='color:#111;'>509B</span>","children":null,"spread":false},{"title":"br.vhd <span style='color:#111;'>526B</span>","children":null,"spread":false},{"title":"alu.vhd <span style='color:#111;'>1.95KB</span>","children":null,"spread":false},{"title":"cm.vhd <span style='color:#111;'>4.80KB</span>","children":null,"spread":false},{"title":"car.vhd <span style='color:#111;'>743B</span>","children":null,"spread":false},{"title":"cpu.qpf <span style='color:#111;'>904B</span>","children":null,"spread":false},{"title":"cbr.vhd <span style='color:#111;'>831B</span>","children":null,"spread":false},{"title":"lpm_ram_dq0.vhd <span style='color:#111;'>7.08KB</span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}]