[{"title":"(3个子文件6KB)UE中显示VHDL、Verilog和SystemVerilog的高亮文件","children":[{"title":"UE的HDL高亮文件","children":[{"title":"vhdl.uew <span style='color:#111;'>1.88KB</span>","children":null,"spread":false},{"title":"systemverilog.uew <span style='color:#111;'>6.07KB</span>","children":null,"spread":false},{"title":"verilog2001.uew <span style='color:#111;'>4.31KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}]