[{"title":"(231个子文件1.48MB)Verilog实现示波器","children":[{"title":"oscilloscope.xdc <span style='color:#111;'>1.79KB</span>","children":null,"spread":false},{"title":"trigger.v <span style='color:#111;'>875B</span>","children":null,"spread":false},{"title":"clock.xci <span style='color:#111;'>65.02KB</span>","children":null,"spread":false},{"title":"debounce.v <span style='color:#111;'>1020B</span>","children":null,"spread":false},{"title":"debounce_0_funcsim.vhdl <span style='color:#111;'>6.63KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]