(70个子文件436KB)VerilogHDl语言实现CPLD-EPC240与电脑的串口通讯QUARTUS逻辑工程源码.zip
用VerilogHDl语言实现CPLD与电脑的串口通讯
serial.pre_map.hdb 11.40KB
serial.sld_design_entry.sci 168B
serial.tis_db_list.ddb 188B
serial.asm_labs.ddb 2.20KB
serial.(0).cnf.cdb 16.32KB
serial.pre_map.cdb 12.70KB
serial.rtlv_sg.cdb 12.62KB
prev_cmp_serial.qmsg 90.69KB
serial.sgdiff.hdb 12.43KB
prev_cmp_serial.asm.qmsg 2.17KB
prev_cmp_serial.tan.qmsg 47.28KB
prev_cmp_serial.fit.qmsg 27.08KB
serial.(0).cnf.hdb 2.91KB
serial.sld_design_entry_dsc.sci 168B
prev_cmp_serial.map.qmsg 13.93KB
serial.rtlv_sg_swap.cdb 192B
serial.sgdiff.cdb 12.73KB
serial.root_partition.map.kpt 38.91KB
serial.tan.summary 1.65KB
serial_assignment_defaults.qdf 26.46KB
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