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基于Tomasulo算法的32位RISC带Cache的流水线CPU设计

上传者: xumo0611 | 上传时间:2017/2/9 18:39:14 | 文件大小:3.43MB | 文件类型:rar
基于Tomasulo算法的32位RISC带Cache的流水线CPU设计
清华大学电子系微机原理课程设计题目。
4人合作完成。
包含CPU的VHDL、Verilog源代码、仿真文件、波形结果、系统框图、实验报告、以及一个简易汇编器的源代码和可执行文件。
Quartus仿真实现了32位RISC微处理器,支持数据处理(包括乘除法),数据传送,子程序调用,中缀及跳转。
时序仿真主频可达70MHz。
采用Tomasulo算法处理指令流水中的数据相关,并提出了一种对Tomasulo就够的改进。
设计了Cache结构提高访存效率。

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评论信息

  • baidu_17176047:
    很详细,具有参考性。2015-11-06
  • baidu_17176047:
    很详细,具有参考性。2015-11-06
  • twq1108:
    清华大学的课程设计,目前准备做与cache实现有关的工作,该项目中包含了多周期流水线、cache、mmu等,比较全面,很有参考价值2014-10-27
  • twq1108:
    清华大学的课程设计,目前准备做与cache实现有关的工作,该项目中包含了多周期流水线、cache、mmu等,比较全面,很有参考价值2014-10-27
  • kurumi_r:
    很不错,值得参考2013-10-24
  • KURUMI_R:
    很不错,值得参考2013-10-24
  • lxyera:
    文档很详细,想写个流水的IP核,参考了一下流水线的实现2013-08-22
  • lxyera:
    文档很详细,想写个流水的IP核,参考了一下流水线的实现2013-08-22
  • peanutyk:
    好东西。如果全是verilog的就更好了2013-06-22
  • peanutyk:
    好东西。如果全是verilog的就更好了2013-06-22

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