[{"title":"(13个子文件99KB)OV7670VHDL图像采集VGA显示","children":[{"title":"ov7670_top_v1_00_d","children":[{"title":"hdl","children":[{"title":"vhdl","children":[{"title":"vga.vhd <span style='color:#111;'>2.79KB</span>","children":null,"spread":false},{"title":"debounce.vhd <span style='color:#111;'>913B</span>","children":null,"spread":false},{"title":"ov7670_controller.vhd <span style='color:#111;'>2.34KB</span>","children":null,"spread":false},{"title":"i2c_sender.vhd <span style='color:#111;'>3.60KB</span>","children":null,"spread":false},{"title":"clocking.vhd <span style='color:#111;'>8.03KB</span>","children":null,"spread":false},{"title":"ov7670_registers.vhd <span style='color:#111;'>4.90KB</span>","children":null,"spread":false},{"title":"ov7670_top.vhd <span style='color:#111;'>4.77KB</span>","children":null,"spread":false},{"title":"ov7670_capture.vhd <span style='color:#111;'>2.58KB</span>","children":null,"spread":false}],"spread":true},{"title":"verilog","children":null,"spread":false}],"spread":true},{"title":"data","children":[{"title":"ov7670_top_v2_1_0.bbd <span style='color:#111;'>502B</span>","children":null,"spread":false},{"title":"ov7670_top_v2_1_0.pao <span style='color:#111;'>726B</span>","children":null,"spread":false},{"title":"ov7670_top_v2_1_0.mpd <span style='color:#111;'>914B</span>","children":null,"spread":false}],"spread":true},{"title":"netlist","children":[{"title":"frame_buffer.ngc <span style='color:#111;'>1.30MB</span>","children":null,"spread":false}],"spread":true},{"title":"devl","children":[{"title":"ipwiz.log <span style='color:#111;'>3.71KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]