Verilog电子表编程实例

[{"title":"（483个子文件7.29MB）Verilog电子表编程实例","children":[{"title":"cpu_jtag_debug_module_sysclk.v <span style='color:#111;'>6.57KB</span>","children":null,"spread":false},{"title":"MyTimer.flow.rpt <span style='color:#111;'>7.68KB</span>","children":null,"spread":false},{"title":"unnamed.ptf.pre_generation_ptf <span style='color:#111;'>49.70KB</span>","children":null,"spread":false},{"title":"unnamed.sopcinfo <span style='color:#111;'>173.64KB</span>","children":null,"spread":false},{"title":"MyTimer.tan.rpt <span style='color:#111;'>625.31KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]