[{"title":"(510个子文件19.05MB)VerilogHDL高级数字设计课件+源码","children":[{"title":"README.txt <span style='color:#111;'>957B</span>","children":null,"spread":false},{"title":"Counter8_prog.v <span style='color:#111;'>1.27KB</span>","children":null,"spread":false},{"title":"FIFO.v <span style='color:#111;'>3.40KB</span>","children":null,"spread":false},{"title":"Row_Signal.v <span style='color:#111;'>645B</span>","children":null,"spread":false},{"title":"top_keypad_FIFO.v <span style='color:#111;'>1.72KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]