(8个子文件16KB)直方图均衡化的Verilog实现,FPGA上实测可用。
transferFunc_ram.v 1.67KB
mlhdlc_heq_FixPt.v.bak 43.95KB
mlhdlc_heq_FixPt_tc.v 2.26KB
SimpleDualPortRAM_256x19b.v 1.57KB
SimpleDualPortRAM_256x19b_block.v 1.60KB
mlhdlc_heq_FixPt_enb_bypass.v 1.68KB
mlhdlc_heq_FixPt.v 43.93KB
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