CRC32算法(FPGA和C言语)

[{"title":"（45个子文件958KB）CRC32算法(FPGA和C语言)","children":[{"title":"CRC_Vertify","children":[{"title":"CRC程序使用说明.vsd <span style='color:#111;'>985.00KB</span>","children":null,"spread":false},{"title":"FPGA_verilog","children":[{"title":"CRC32_D8_AAL5_tb.v <span style='color:#111;'>1.65KB</span>","children":null,"spread":false},{"title":"CRC32_D32_AAL5_tb.v <span style='color:#111;'>1.55KB</span>","children":null,"spread":false},{"title":"transcript <span style='color:#111;'>391B</span>","children":null,"spread":false},{"title":"CRC32_D32_AAL5.v <span style='color:#111;'>8.18KB</span>","children":null,"spread":false},{"title":"Test_CRC_01.m <span style='color:#111;'>451B</span>","children":null,"spread":false},{"title":"CRC32_D8_AAL5.v <span style='color:#111;'>3.24KB</span>","children":null,"spread":false},{"title":"test.mpf <span style='color:#111;'>74.00KB</span>","children":null,"spread":false},{"title":"test.cr.mti <span style='color:#111;'>1.35KB</span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'>64.00KB</span>","children":null,"spread":false},{"title":"work","children":[{"title":"@c@r@c32_@d8_@a@a@l5_tb","children":[{"title":"_primary.vhd <span style='color:#111;'>92B</span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'>11.32KB</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>1.32KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>3.50KB</span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'>3.09KB</span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'>2.38KB</span>","children":null,"spread":false},{"title":"@c@r@c32_@d32_@a@a@l5","children":[{"title":"_primary.vhd <span style='color:#111;'>422B</span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'>182.66KB</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>14.41KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>47.48KB</span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'>9.02KB</span>","children":null,"spread":false}],"spread":false},{"title":"@c@r@c32_@d32_@a@a@l5_tb","children":[{"title":"_primary.vhd <span style='color:#111;'>94B</span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'>9.57KB</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>1.08KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>3.21KB</span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'>2.62KB</span>","children":null,"spread":false}],"spread":false},{"title":"_temp","children":null,"spread":false},{"title":"@c@r@c32_@d8_@a@a@l5","children":[{"title":"_primary.vhd <span style='color:#111;'>419B</span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'>56.16KB</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>4.86KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>15.34KB</span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'>4.33KB</span>","children":null,"spread":false}],"spread":false},{"title":"_vmake <span style='color:#111;'>26B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"CDemo","children":[{"title":"Demo1","children":[{"title":"Demo1.dsw <span style='color:#111;'>518B</span>","children":null,"spread":false},{"title":"Demo1.opt <span style='color:#111;'>52.50KB</span>","children":null,"spread":false},{"title":"Debug","children":[{"title":"crc32.obj <span style='color:#111;'>4.05KB</span>","children":null,"spread":false},{"title":"vc60.pdb <span style='color:#111;'>44.00KB</span>","children":null,"spread":false},{"title":"Demo1.pch <span style='color:#111;'>180.44KB</span>","children":null,"spread":false},{"title":"Demo1.ilk <span style='color:#111;'>175.87KB</span>","children":null,"spread":false},{"title":"vc60.idb <span style='color:#111;'>33.00KB</span>","children":null,"spread":false},{"title":"Demo1.exe <span style='color:#111;'>168.08KB</span>","children":null,"spread":false},{"title":"Demo1.pdb <span style='color:#111;'>417.00KB</span>","children":null,"spread":false}],"spread":true},{"title":"Demo1.dsp <span style='color:#111;'>4.17KB</span>","children":null,"spread":false},{"title":"Demo1.plg <span style='color:#111;'>244B</span>","children":null,"spread":false},{"title":"crc32.c <span style='color:#111;'>3.84KB</span>","children":null,"spread":false},{"title":"Demo1.ncb <span style='color:#111;'>41.00KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true}]