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VHDL频率计的设计

上传者: renyanyang1989 | 上传时间:2017/11/16 22:38:42 | 文件大小:355KB | 文件类型:rar
VHDL频率计的设计
VHDL频率计,可以最小频率是1HZ,最大由FPGA的芯片限制。
可以精确测量方波频率。

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