/ 基于Verilog的三人抢答器

基于Verilog的三人抢答器

verilog

基于Verilog的三人抢答器
实现的功能：1.设计一个十秒的倒计时计时器用于选手看题准备并且设计一个60秒的倒计时用于答题。
2.设计电路实现三人抢答。
3.实现用LCD1602显示当前比赛进行的状态。
各个状态如下：（1）抢答前显示开始抢答和该问题为第几个问题（共有5题）：“Begin！”“Question-x”。
（2）若在十秒的该抢答时间内无人抢答，显示失败，下一题。
“Failtoquiz!“”Next！“。
（3）抢答后显示抢答选手姓名，如：“Respondent”“Zhangsan”。
（4）选手抢到题后该选手指示灯亮，回答完毕或回答时间到熄灭。
（5）若选手在六十秒的回答时间内未完成回答则显示失败。
“Failure！“若在有效的十秒内回答完毕则由裁判对回答的正误判断分别显示“Congratulation！+10““Failure！“。
如此反复，共进行五次。
（6）当完成竞赛总数（共5题）题目时，显示竞赛结束。
“Endofthequiz!”4.设计计分器对选手的得分进行及时的显示。
（答对一题得一分，答错或回答超时扣一分） 本软件ID:10628975

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