基于FPGA与MATLAB的fir滤波器实现（Verilog）

[{"title":"（173个子文件8.02MB）基于FPGA与MATLAB的fir滤波器实现（Verilog）","children":[{"title":"FIR.rar <span style='color:#111;'>5.83MB</span>","children":null,"spread":false},{"title":"mult.v.bak <span style='color:#111;'>82B</span>","children":null,"spread":false},{"title":"fir_parr_8.cdf <span style='color:#111;'>327B</span>","children":null,"spread":false},{"title":"myrom_bb.v <span style='color:#111;'>5.02KB</span>","children":null,"spread":false},{"title":"fir_parr_8.sdc <span style='color:#111;'>3.14KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]