美信OneWire总线IPCore(带验证激励)

[{"title":"（59个子文件55KB）美信OneWire总线IPCore(带验证激励)","children":[{"title":"design","children":[{"title":"vhdl_src","children":[{"title":"ds1wm","children":[{"title":"one_wire_io.vhd <span style='color:#111;'>2.63KB</span>","children":null,"spread":false},{"title":"ds1wm.vhd <span style='color:#111;'>13.84KB</span>","children":null,"spread":false},{"title":"onewiremaster.vhd <span style='color:#111;'>57.15KB</span>","children":null,"spread":false},{"title":"one_wire_interface.vhd <span style='color:#111;'>14.88KB</span>","children":null,"spread":false},{"title":"clk_prescaler.vhd <span style='color:#111;'>7.86KB</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"verilog_src","children":[{"title":"ds1wm","children":[{"title":"ds1wm.v <span style='color:#111;'>3.75KB</span>","children":null,"spread":false},{"title":"one_wire_interface.v <span style='color:#111;'>13.25KB</span>","children":null,"spread":false},{"title":"clk_prescaler.v <span style='color:#111;'>5.37KB</span>","children":null,"spread":false},{"title":"one_wire_io.v <span style='color:#111;'>2.32KB</span>","children":null,"spread":false},{"title":"onewiremaster.v <span style='color:#111;'>48.26KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"README <span style='color:#111;'>998B</span>","children":null,"spread":false},{"title":"verification","children":[{"title":"verilog_src","children":[{"title":"tests","children":[{"title":"single_search_rom","children":[{"title":"stimulus.inc <span style='color:#111;'>983B</span>","children":null,"spread":false},{"title":"README <span style='color:#111;'>597B</span>","children":null,"spread":false},{"title":"nc_rundir","children":[{"title":"design_vhdl_src_files.lst <span style='color:#111;'>270B</span>","children":null,"spread":false},{"title":"tb_src_files.lst <span style='color:#111;'>306B</span>","children":null,"spread":false},{"title":"ncsim.key <span style='color:#111;'>5B</span>","children":null,"spread":false},{"title":"hdl.var <span style='color:#111;'>38B</span>","children":null,"spread":false},{"title":"run.csh <span style='color:#111;'>623B</span>","children":null,"spread":false},{"title":"probe.tcl <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"design_verilog_src_files.lst <span style='color:#111;'>275B</span>","children":null,"spread":false},{"title":"cds.lib <span style='color:#111;'>94B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"cmd_recognition","children":[{"title":"stimulus.inc <span style='color:#111;'>10.88KB</span>","children":null,"spread":false},{"title":"README <span style='color:#111;'>613B</span>","children":null,"spread":false},{"title":"nc_rundir","children":[{"title":"design_vhdl_src_files.lst <span style='color:#111;'>270B</span>","children":null,"spread":false},{"title":"tb_src_files.lst <span style='color:#111;'>306B</span>","children":null,"spread":false},{"title":"ncsim.key <span style='color:#111;'>5B</span>","children":null,"spread":false},{"title":"hdl.var <span style='color:#111;'>38B</span>","children":null,"spread":false},{"title":"run.csh <span style='color:#111;'>623B</span>","children":null,"spread":false},{"title":"probe.tcl <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"design_verilog_src_files.lst <span style='color:#111;'>275B</span>","children":null,"spread":false},{"title":"cds.lib <span style='color:#111;'>94B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"scratchpad_integrity","children":[{"title":"stimulus.inc <span style='color:#111;'>1.62KB</span>","children":null,"spread":false},{"title":"README <span style='color:#111;'>621B</span>","children":null,"spread":false},{"title":"nc_rundir","children":[{"title":"design_vhdl_src_files.lst <span style='color:#111;'>270B</span>","children":null,"spread":false},{"title":"tb_src_files.lst <span style='color:#111;'>306B</span>","children":null,"spread":false},{"title":"ncsim.key <span style='color:#111;'>5B</span>","children":null,"spread":false},{"title":"hdl.var <span style='color:#111;'>38B</span>","children":null,"spread":false},{"title":"run.csh <span style='color:#111;'>623B</span>","children":null,"spread":false},{"title":"probe.tcl <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"design_verilog_src_files.lst <span style='color:#111;'>275B</span>","children":null,"spread":false},{"title":"cds.lib <span style='color:#111;'>94B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"multi_ow_network","children":[{"title":"stimulus.inc <span style='color:#111;'>1.39KB</span>","children":null,"spread":false},{"title":"README <span style='color:#111;'>654B</span>","children":null,"spread":false},{"title":"nc_rundir","children":[{"title":"design_vhdl_src_files.lst <span style='color:#111;'>270B</span>","children":null,"spread":false},{"title":"tb_src_files.lst <span style='color:#111;'>306B</span>","children":null,"spread":false},{"title":"ncsim.key <span style='color:#111;'>5B</span>","children":null,"spread":false},{"title":"hdl.var <span style='color:#111;'>38B</span>","children":null,"spread":false},{"title":"run.csh <span style='color:#111;'>641B</span>","children":null,"spread":false},{"title":"probe.tcl <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"design_verilog_src_files.lst <span style='color:#111;'>275B</span>","children":null,"spread":false},{"title":"cds.lib <span style='color:#111;'>94B</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"testbench","children":[{"title":"tb_ds1wm","children":[{"title":"tc_ds1wm.v <span style='color:#111;'>2.25KB</span>","children":null,"spread":false},{"title":"tb_ds1wm.v <span style='color:#111;'>844B</span>","children":null,"spread":false}],"spread":true},{"title":"scoreboard","children":[{"title":"scoreboard.v <span style='color:#111;'>6.21KB</span>","children":null,"spread":false}],"spread":true},{"title":"clkgen","children":[{"title":"clkgen.v <span style='color:#111;'>3.19KB</span>","children":null,"spread":false}],"spread":true},{"title":"ow_slave","children":[{"title":"iox.v <span style='color:#111;'>11.76KB</span>","children":null,"spread":false},{"title":"cmd_ctrl.v <span style='color:#111;'>7.65KB</span>","children":null,"spread":false},{"title":"ow_slave.v <span style='color:#111;'>1.67KB</span>","children":null,"spread":false}],"spread":true},{"title":"cpu_bfm","children":[{"title":"cpu_bfm.v <span style='color:#111;'>20.45KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true}],"spread":true}]