七分频quartus实现verilog

[{"title":"（103个子文件1.05MB）七分频quartus实现verilog","children":[{"title":"divide_7.flow.rpt <span style='color:#111;'>7.53KB</span>","children":null,"spread":false},{"title":"divide_7.qws <span style='color:#111;'>624B</span>","children":null,"spread":false},{"title":"divide_7.sim.rpt <span style='color:#111;'>12.03KB</span>","children":null,"spread":false},{"title":"divide_7.sof <span style='color:#111;'>484.90KB</span>","children":null,"spread":false},{"title":"divide_7.fit.rpt <span style='color:#111;'>162.17KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]