FPGA开发例程

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style='color:#111;'>360B</span>","children":null,"spread":false}],"spread":true},{"title":"rom_controller.qip <span style='color:#111;'>0B</span>","children":null,"spread":false},{"title":"fifo_controller.v <span style='color:#111;'>6.52KB</span>","children":null,"spread":false},{"title":"fifo_controller.qip <span style='color:#111;'>388B</span>","children":null,"spread":false},{"title":"fifo_controller_bb.v <span style='color:#111;'>5.54KB</span>","children":null,"spread":false},{"title":"fifo_controller_inst.v <span style='color:#111;'>222B</span>","children":null,"spread":false}],"spread":true},{"title":"rom","children":[{"title":"greybox_tmp","children":[{"title":"cbx_args.txt <span style='color:#111;'>356B</span>","children":null,"spread":false}],"spread":true},{"title":"rom_controller.qip <span style='color:#111;'>392B</span>","children":null,"spread":false},{"title":"rom_controller_bb.v <span style='color:#111;'>5.11KB</span>","children":null,"spread":false},{"title":"rom_controller.v <span style='color:#111;'>6.56KB</span>","children":null,"spread":false},{"title":"rom_controller_inst.v <span style='color:#111;'>110B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"cy4.qws <span style='color:#111;'>1.78KB</span>","children":null,"spread":false},{"title":"cy4.qpf <span style='color:#111;'>1.24KB</span>","children":null,"spread":false},{"title":"PLLJ_PLLSPE_INFO.txt <span style='color:#111;'>156B</span>","children":null,"spread":false},{"title":"cy4_assignment_defaults.qdf <span style='color:#111;'>48.64KB</span>","children":null,"spread":false},{"title":"source_code","children":[{"title":"greybox_tmp","children":[{"title":"cbx_args.txt <span style='color:#111;'>356B</span>","children":null,"spread":false}],"spread":true},{"title":"my_uart_rx.v <span style='color:#111;'>3.59KB</span>","children":null,"spread":false},{"title":"test_timing.v <span style='color:#111;'>4.14KB</span>","children":null,"spread":false},{"title":"rtc_top.v <span style='color:#111;'>2.79KB</span>","children":null,"spread":false},{"title":"iic_controller.v <span style='color:#111;'>6.43KB</span>","children":null,"spread":false},{"title":"seg7.v <span style='color:#111;'>3.10KB</span>","children":null,"spread":false},{"title":"key_check.v <span style='color:#111;'>2.39KB</span>","children":null,"spread":false},{"title":"sram_controller.v <span style='color:#111;'>4.31KB</span>","children":null,"spread":false},{"title":"led_controller.v <span style='color:#111;'>1.32KB</span>","children":null,"spread":false},{"title":"beep.v <span style='color:#111;'>1.12KB</span>","children":null,"spread":false},{"title":"speed_setting.v <span style='color:#111;'>1.84KB</span>","children":null,"spread":false},{"title":"lcd_controller.v <span style='color:#111;'>9.12KB</span>","children":null,"spread":false},{"title":"cy4.v <span style='color:#111;'>11.65KB</span>","children":null,"spread":false},{"title":"adc_controller.v <span style='color:#111;'>3.41KB</span>","children":null,"spread":false},{"title":"rom_init.mif <span style='color:#111;'>12.51KB</span>","children":null,"spread":false},{"title":"dac_controller.v <span style='color:#111;'>4.40KB</span>","children":null,"spread":false},{"title":"para_define.v <span style='color:#111;'>477B</span>","children":null,"spread":false},{"title":"rtc_controller.v <span style='color:#111;'>6.24KB</span>","children":null,"spread":false},{"title":"my_uart_tx.v <span style='color:#111;'>1.96KB</span>","children":null,"spread":false}],"spread":false},{"title":"simulation","children":[{"title":"modelsim","children":[{"title":"cy4_v.sdo <span style='color:#111;'>724.02KB</span>","children":null,"spread":false},{"title":"cy4_min_1200mv_0c_fast.vo <span style='color:#111;'>1.13MB</span>","children":null,"spread":false},{"title":"cy4_8_1200mv_0c_slow.vo <span style='color:#111;'>1.13MB</span>","children":null,"spread":false},{"title":"cy4_8_1200mv_0c_v_slow.sdo <span style='color:#111;'>723.37KB</span>","children":null,"spread":false},{"title":"cy4_modelsim.xrf <span style='color:#111;'>137.72KB</span>","children":null,"spread":false},{"title":"cy4.sft <span style='color:#111;'>323B</span>","children":null,"spread":false},{"title":"cy4_8_1200mv_85c_v_slow.sdo <span style='color:#111;'>724.02KB</span>","children":null,"spread":false},{"title":"cy4_8_1200mv_85c_slow.vo <span style='color:#111;'>1.13MB</span>","children":null,"spread":false},{"title":"cy4_min_1200mv_0c_v_fast.sdo <span style='color:#111;'>705.40KB</span>","children":null,"spread":false},{"title":"cy4.vo <span style='color:#111;'>1.13MB</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"output_files","children":[{"title":"cy4.cdf <span style='color:#111;'>378B</span>","children":null,"spread":false},{"title":"cy4.sof <span style='color:#111;'>350.23KB</span>","children":null,"spread":false},{"title":"cy4.fit.summary <span style='color:#111;'>609B</span>","children":null,"spread":false},{"title":"cy4.fit.smsg <span style='color:#111;'>703B</span>","children":null,"spread":false},{"title":"cy4.fit.rpt <span style='color:#111;'>518.78KB</span>","children":null,"spread":false},{"title":"cy4.map.summary <span style='color:#111;'>469B</span>","children":null,"spread":false},{"title":"cy4_test.jic <span style='color:#111;'>512.22KB</span>","children":null,"spread":false},{"title":"cy4.jdi <span style='color:#111;'>221B</span>","children":null,"spread":false},{"title":"cy4.map.rpt <span style='color:#111;'>176.46KB</span>","children":null,"spread":false},{"title":"cy4.sta.rpt <span style='color:#111;'>1.04MB</span>","children":null,"spread":false},{"title":"cy4.pin <span style='color:#111;'>19.70KB</span>","children":null,"spread":false},{"title":"cy4.flow.rpt <span style='color:#111;'>10.57KB</span>","children":null,"spread":false},{"title":"cy4.asm.rpt <span style='color:#111;'>6.98KB</span>","children":null,"spread":false},{"title":"cy4_test.map <span style='color:#111;'>189B</span>","children":null,"spread":false},{"title":"cy4.eda.rpt <span style='color:#111;'>7.44KB</span>","children":null,"spread":false},{"title":"cy4.sta.summary <span style='color:#111;'>2.95KB</span>","children":null,"spread":false},{"title":"cy4.done <span style='color:#111;'>26B</span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}]