用verilog写得一个双口ram模块

[{"title":"（823个子文件2.15MB）用verilog写得一个双口ram模块","children":[{"title":"reg_dpram.pin <span style='color:#111;'>26.46KB</span>","children":null,"spread":false},{"title":"reg_dpram.sof <span style='color:#111;'>235.13KB</span>","children":null,"spread":false},{"title":"reg_dpram.sta.rpt <span style='color:#111;'>84.45KB</span>","children":null,"spread":false},{"title":"reg_dpram.eda.rpt <span style='color:#111;'>6.31KB</span>","children":null,"spread":false},{"title":"reg_dpram.cmp0.ddb <span style='color:#111;'>86.73KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]