I2C总线的verilog代码

[{"title":"（79个子文件497KB）I2C总线的verilog代码","children":[{"title":"i2c","children":[{"title":"rtl","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>25B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>8B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"vhdl","children":[{"title":"i2c_master_byte_ctrl.vhd <span style='color:#111;'>12.55KB</span>","children":null,"spread":false},{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>293B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>13B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"i2c_master_bit_ctrl.vhd <span style='color:#111;'>17.74KB</span>","children":null,"spread":false},{"title":"I2C.VHD <span style='color:#111;'>13.22KB</span>","children":null,"spread":false},{"title":"i2c_master_top.vhd <span style='color:#111;'>13.13KB</span>","children":null,"spread":false},{"title":"readme <span style='color:#111;'>789B</span>","children":null,"spread":false},{"title":"tst_ds1621.vhd <span style='color:#111;'>6.80KB</span>","children":null,"spread":false}],"spread":true},{"title":"verilog","children":[{"title":"i2c_master_byte_ctrl.v <span style='color:#111;'>10.30KB</span>","children":null,"spread":false},{"title":"i2c_master_top.v <span style='color:#111;'>9.87KB</span>","children":null,"spread":false},{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>259B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>16B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"i2c_master_bit_ctrl.v <span style='color:#111;'>16.90KB</span>","children":null,"spread":false},{"title":"i2c_master_defines.v <span style='color:#111;'>3.14KB</span>","children":null,"spread":false},{"title":"timescale.v <span style='color:#111;'>23B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"bench","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>14B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>10B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"verilog","children":[{"title":"spi_slave_model.v <span style='color:#111;'>3.84KB</span>","children":null,"spread":false},{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>200B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>18B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"wb_master_model.v <span style='color:#111;'>5.44KB</span>","children":null,"spread":false},{"title":"i2c_slave_model.v <span style='color:#111;'>11.15KB</span>","children":null,"spread":false},{"title":"tst_bench_top.v <span style='color:#111;'>14.09KB</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>102B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>4B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"documentation","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>2B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>18B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"software","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>28B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>13B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"include","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>50B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>21B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"oc_i2c_master.h <span style='color:#111;'>5.59KB</span>","children":null,"spread":false}],"spread":true},{"title":"drivers","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>2B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>21B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"vhdl","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>2B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>9B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"verilog","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>2B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>12B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"doc","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>59B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>8B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"src","children":[{"title":"I2C_specs.doc <span style='color:#111;'>454.00KB</span>","children":null,"spread":false},{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>51B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>12B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"i2c_specs.pdf <span style='color:#111;'>206.51KB</span>","children":null,"spread":false}],"spread":true},{"title":"sim","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>18B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>8B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"i2c_verilog","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>10B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>20B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":true},{"title":"run","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>198B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>24B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":false},{"title":"ncverilog.key <span style='color:#111;'>5B</span>","children":null,"spread":false},{"title":"ncverilog.log <span style='color:#111;'>4.59KB</span>","children":null,"spread":false},{"title":"waves","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>2B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>30B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"INCA_libs","children":[{"title":"CVS","children":[{"title":"Entries <span style='color:#111;'>2B</span>","children":null,"spread":false},{"title":"Repository <span style='color:#111;'>34B</span>","children":null,"spread":false},{"title":"Root <span style='color:#111;'>14B</span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"bench.vcd <span style='color:#111;'>5.07MB</span>","children":null,"spread":false},{"title":"run <span style='color:#111;'>597B</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true}],"spread":true}]