FPGA驱动DS18B20_Verilog

[{"title":"（373个子文件9.18MB）FPGA驱动DS18B20_Verilog","children":[{"title":"clk_1ms.v.bak <span style='color:#111;'>314B</span>","children":null,"spread":false},{"title":"stp1.stp <span style='color:#111;'>23.77KB</span>","children":null,"spread":false},{"title":"rel.tcl <span style='color:#111;'>1.19KB</span>","children":null,"spread":false},{"title":"clk_1us.v.bak <span style='color:#111;'>276B</span>","children":null,"spread":false},{"title":"data_cahange.v <span style='color:#111;'>1.48KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]