LDPC编码Verilog代码

[{"title":"（30个子文件63KB）LDPC编码Verilog代码","children":[{"title":"verilog_rtl","children":[{"title":"rtlsim","children":[{"title":"run_dir","children":[{"title":"run.bat <span style='color:#111;'>55B</span>","children":null,"spread":false}],"spread":true},{"title":"lq.csv <span style='color:#111;'>28.97KB</span>","children":null,"spread":false},{"title":"debussy","children":[{"title":"cnu.rc <span style='color:#111;'>5.61KB</span>","children":null,"spread":false},{"title":"run_deb.bat <span style='color:#111;'>61B</span>","children":null,"spread":false},{"title":"cnu2.rc <span style='color:#111;'>3.87KB</span>","children":null,"spread":false},{"title":"ref.f <span style='color:#111;'>392B</span>","children":null,"spread":false},{"title":"hdl.f <span style='color:#111;'>376B</span>","children":null,"spread":false},{"title":"run_ldpc.bat <span style='color:#111;'>36B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"tb","children":[{"title":"pattern","children":[{"title":"data_in.dat <span style='color:#111;'>22.43KB</span>","children":null,"spread":false}],"spread":true},{"title":"ldpc_tb.v <span style='color:#111;'>1.96KB</span>","children":null,"spread":false}],"spread":true},{"title":"rtl","children":[{"title":"rd_cell.v <span style='color:#111;'>1.11KB</span>","children":null,"spread":false},{"title":"data_cell2.v <span style='color:#111;'>1.16KB</span>","children":null,"spread":false},{"title":"addr_gen.v <span style='color:#111;'>27.89KB</span>","children":null,"spread":false},{"title":"data_cell.v <span style='color:#111;'>922B</span>","children":null,"spread":false},{"title":"sram2p768x52.v <span style='color:#111;'>1.70KB</span>","children":null,"spread":false},{"title":"debug.v <span style='color:#111;'>13.84KB</span>","children":null,"spread":false},{"title":"ldpc_dec.v <span style='color:#111;'>1.53KB</span>","children":null,"spread":false},{"title":"sram256x8.v <span style='color:#111;'>1.42KB</span>","children":null,"spread":false},{"title":"sram2p256x8.v <span style='color:#111;'>1.69KB</span>","children":null,"spread":false},{"title":"data_cell1.v <span style='color:#111;'>1.16KB</span>","children":null,"spread":false},{"title":"ldpc_ctrl.v <span style='color:#111;'>10.08KB</span>","children":null,"spread":false},{"title":"rd_seq.v <span style='color:#111;'>3.16KB</span>","children":null,"spread":false},{"title":"ldpc.v <span style='color:#111;'>31.41KB</span>","children":null,"spread":false},{"title":"ldpc_vtc.v <span style='color:#111;'>15.26KB</span>","children":null,"spread":false},{"title":"comp_cell.v <span style='color:#111;'>11.93KB</span>","children":null,"spread":false},{"title":"wr_cell.v <span style='color:#111;'>1.58KB</span>","children":null,"spread":false},{"title":"out_table.v <span style='color:#111;'>189.19KB</span>","children":null,"spread":false},{"title":"vtc_cell.v <span style='color:#111;'>2.39KB</span>","children":null,"spread":false},{"title":"data_comp.v <span style='color:#111;'>61.99KB</span>","children":null,"spread":false},{"title":"lr_cell.v <span style='color:#111;'>3.36KB</span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}]