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VHDL数字频率计设计

上传者: ding44211 | 上传时间:2018/2/18 23:28:57 | 文件大小:162KB | 文件类型:rar
VHDL数字频率计设计
实验课需求用到且调试通过~LIBRARYIEEE;--有时钟使能的十进制计数器USEIEEE.STD_LOGIC_1164.ALL;ENTITYCNT10ISPORT(CLK:INSTD_LOGIC;--计数时钟信号CLR:INSTD_LOGIC;--清零信号ENA:INSTD_LOGIC;--计数使能信号CQ:OUTINTEGERRANGE0TO15;--4位计数结果输出CARRY_OUT:OUTSTD_LOGIC);--计数进位ENDCNT10;。




本软件ID:2914133

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评论信息

  • anyongqian123:
    做为一个作业挺适合的,对初学者有帮助2012-03-17

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