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verilog语言实现数字钟的设计

上传者: AMY1024 | 上传时间:2023/8/18 16:12:53 | 文件大小:272KB | 文件类型:rar
verilog语言实现数字钟的设计
采用verilog语言实现数字钟的设计,采用quarters2语言环境。
本软件ID:2356788

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评论信息

  • laozhoujzl:
    能用的,代码蛮清晰的2013-02-16
  • laozhoujzl:
    能用的,代码蛮清晰的2013-02-16
  • z85343619:
    很好,可以烧到fpga上直接用2012-08-01
  • z85343619:
    很好,可以烧到fpga上直接用2012-08-01

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