VerilogHDL在FPGA中完成的数字时钟

[{"title":"（61个子文件308KB）VerilogHDL在FPGA中实现的数字时钟","children":[{"title":"数字时钟","children":[{"title":"clock.asm.rpt <span style='color:#111;'>6.53KB</span>","children":null,"spread":false},{"title":"clock.fit.rpt <span style='color:#111;'>54.49KB</span>","children":null,"spread":false},{"title":"clock.fit.eqn <span style='color:#111;'>46.31KB</span>","children":null,"spread":false},{"title":"clock.map.summary <span style='color:#111;'>288B</span>","children":null,"spread":false},{"title":"clock.pin <span style='color:#111;'>14.37KB</span>","children":null,"spread":false},{"title":"clock.tan.summary <span style='color:#111;'>984B</span>","children":null,"spread":false},{"title":"clock.tan.rpt <span style='color:#111;'>93.80KB</span>","children":null,"spread":false},{"title":"cmp_state.ini <span style='color:#111;'>3B</span>","children":null,"spread":false},{"title":"clock.qpf <span style='color:#111;'>945B</span>","children":null,"spread":false},{"title":"db","children":[{"title":"clock.pre_map.cdb <span style='color:#111;'>8.61KB</span>","children":null,"spread":false},{"title":"clock.sgdiff.hdb <span style='color:#111;'>8.55KB</span>","children":null,"spread":false},{"title":"clock.tan.qmsg <span style='color:#111;'>28.79KB</span>","children":null,"spread":false},{"title":"clock.sgdiff.cdb <span style='color:#111;'>9.53KB</span>","children":null,"spread":false},{"title":"clock.cbx.xml <span style='color:#111;'>87B</span>","children":null,"spread":false},{"title":"clock.eco.cdb <span style='color:#111;'>141B</span>","children":null,"spread":false},{"title":"clock.(0).cnf.hdb <span style='color:#111;'>2.98KB</span>","children":null,"spread":false},{"title":"clock.fit.qmsg <span style='color:#111;'>17.31KB</span>","children":null,"spread":false},{"title":"clock.hier_info <span style='color:#111;'>4.38KB</span>","children":null,"spread":false},{"title":"clock.cmp0.ddb <span style='color:#111;'>59.61KB</span>","children":null,"spread":false},{"title":"clock.rtlv_sg_swap.cdb <span style='color:#111;'>158B</span>","children":null,"spread":false},{"title":"clock.syn_hier_info <span style='color:#111;'>0B</span>","children":null,"spread":false},{"title":"add_sub_bph.tdf <span style='color:#111;'>7.22KB</span>","children":null,"spread":false},{"title":"clock.cmp.rdb <span style='color:#111;'>18.45KB</span>","children":null,"spread":false},{"title":"clock.cmp.logdb <span style='color:#111;'>4B</span>","children":null,"spread":false},{"title":"clock.asm_labs.ddb <span style='color:#111;'>9.45KB</span>","children":null,"spread":false},{"title":"clock.sld_design_entry.sci <span style='color:#111;'>134B</span>","children":null,"spread":false},{"title":"clock.map.logdb <span style='color:#111;'>4B</span>","children":null,"spread":false},{"title":"clock.rtlv_sg.cdb <span style='color:#111;'>8.58KB</span>","children":null,"spread":false},{"title":"clock.map.hdb <span style='color:#111;'>8.23KB</span>","children":null,"spread":false},{"title":"clock.pre_map.hdb <span style='color:#111;'>7.35KB</span>","children":null,"spread":false},{"title":"add_sub_onh.tdf <span style='color:#111;'>2.72KB</span>","children":null,"spread":false},{"title":"clock.cmp.cdb <span style='color:#111;'>36.51KB</span>","children":null,"spread":false},{"title":"clock_cmp.qrpt <span style='color:#111;'>0B</span>","children":null,"spread":false},{"title":"clock.map.qmsg <span style='color:#111;'>19.99KB</span>","children":null,"spread":false},{"title":"clock.hif <span style='color:#111;'>562B</span>","children":null,"spread":false},{"title":"clock.psp <span style='color:#111;'>0B</span>","children":null,"spread":false},{"title":"clock.rtlv.hdb <span style='color:#111;'>7.31KB</span>","children":null,"spread":false},{"title":"clock.map.cdb <span style='color:#111;'>10.40KB</span>","children":null,"spread":false},{"title":"clock.(0).cnf.cdb <span style='color:#111;'>10.16KB</span>","children":null,"spread":false},{"title":"clock.db_info <span style='color:#111;'>136B</span>","children":null,"spread":false},{"title":"clock.sld_design_entry_dsc.sci <span style='color:#111;'>134B</span>","children":null,"spread":false},{"title":"clock.cmp.tdb <span style='color:#111;'>36.20KB</span>","children":null,"spread":false},{"title":"clock.dbp <span style='color:#111;'>0B</span>","children":null,"spread":false},{"title":"clock.signalprobe.cdb <span style='color:#111;'>314B</span>","children":null,"spread":false},{"title":"clock.cmp.kpt <span style='color:#111;'>205B</span>","children":null,"spread":false},{"title":"clock.cmp.hdb <span style='color:#111;'>8.93KB</span>","children":null,"spread":false},{"title":"clock.asm.qmsg <span style='color:#111;'>1.74KB</span>","children":null,"spread":false}],"spread":false},{"title":"clock.v.bak <span style='color:#111;'>2.97KB</span>","children":null,"spread":false},{"title":"clock.map.eqn <span style='color:#111;'>45.25KB</span>","children":null,"spread":false},{"title":"clock.flow.rpt <span style='color:#111;'>4.24KB</span>","children":null,"spread":false},{"title":"clock.qsf <span style='color:#111;'>3.01KB</span>","children":null,"spread":false},{"title":"clock_assignment_defaults.qdf <span style='color:#111;'>26.46KB</span>","children":null,"spread":false},{"title":"clock.qws <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"clock.done <span style='color:#111;'>26B</span>","children":null,"spread":false},{"title":"clock.fit.smsg <span style='color:#111;'>334B</span>","children":null,"spread":false},{"title":"clock.dpf <span style='color:#111;'>239B</span>","children":null,"spread":false},{"title":"clock.cdf <span style='color:#111;'>304B</span>","children":null,"spread":false},{"title":"clock.pof <span style='color:#111;'>7.67KB</span>","children":null,"spread":false},{"title":"clock.map.rpt <span style='color:#111;'>22.53KB</span>","children":null,"spread":false},{"title":"clock.v <span style='color:#111;'>2.85KB</span>","children":null,"spread":false},{"title":"clock.fit.summary <span style='color:#111;'>362B</span>","children":null,"spread":false}],"spread":false}],"spread":true}]