[{"title":"(45个子文件1.16MB)FilterPro+Tina设计并实现的带通滤波器(内含PCB)","children":[{"title":"带通滤波器","children":[{"title":"History","children":[{"title":"2018-9-20.~(1).PrjPcb.Zip <span style='color:#111;'>3.73KB</span>","children":null,"spread":false}],"spread":true},{"title":"2018-9-20.PcbDocPreview <span style='color:#111;'>39.40KB</span>","children":null,"spread":false},{"title":"2018-9-20.PrjPcb <span style='color:#111;'>31.59KB</span>","children":null,"spread":false},{"title":"ProjectLogsfor2018-9-20","children":[{"title":"2018-9-20PCBECO2018-9-2511-15-45.LOG <span style='color:#111;'>10.17KB</span>","children":null,"spread":false},{"title":"PCB1PCBECO2018-11-2815-50-43.LOG <span style='color:#111;'>230B</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2511-17-11.LOG <span style='color:#111;'>322B</span>","children":null,"spread":false},{"title":"2018-9-20SCHECO2018-11-2610-39-41.LOG <span style='color:#111;'>1.31KB</span>","children":null,"spread":false},{"title":"PCB1PCBECO2018-11-2814-52-47.LOG <span style='color:#111;'>115B</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-12-1121-39-07.LOG <span style='color:#111;'>459B</span>","children":null,"spread":false},{"title":"2018-9-20SCHECO2018-9-2511-15-24.LOG <span style='color:#111;'>3.18KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2511-11-51.LOG <span style='color:#111;'>5.91KB</span>","children":null,"spread":false},{"title":"PCB1PCBECO2018-11-2815-44-55.LOG <span style='color:#111;'>9.83KB</span>","children":null,"spread":false},{"title":"2018-9-20SCHECO2018-12-1119-51-14.LOG <span style='color:#111;'>1.71KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2611-14-11.LOG <span style='color:#111;'>488B</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2521-27-09.LOG <span style='color:#111;'>119B</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2511-18-33.LOG <span style='color:#111;'>800B</span>","children":null,"spread":false},{"title":"PCB1PCBECO2018-11-2815-50-01.LOG <span style='color:#111;'>9.72KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-11-2815-54-15.LOG <span style='color:#111;'>10.50KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2611-17-40.LOG <span style='color:#111;'>559B</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-12-1120-29-48.LOG <span style='color:#111;'>111B</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-12-1120-01-36.LOG <span style='color:#111;'>7.62KB</span>","children":null,"spread":false},{"title":"PCB1PCBECO2018-11-2815-47-02.LOG <span style='color:#111;'>9.72KB</span>","children":null,"spread":false},{"title":"PCB1PCBECO2018-11-2815-51-49.LOG <span style='color:#111;'>10.18KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2511-19-43.LOG <span style='color:#111;'>10.61KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-11-2816-01-55.LOG <span style='color:#111;'>1.17KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2522-23-39.LOG <span style='color:#111;'>117B</span>","children":null,"spread":false},{"title":"2018-9-20SCHECO2018-11-2815-09-05.LOG <span style='color:#111;'>1.04KB</span>","children":null,"spread":false},{"title":"PCB1PCBECO2018-11-2814-50-20.LOG <span style='color:#111;'>2.82KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-12-1120-29-16.LOG <span style='color:#111;'>355B</span>","children":null,"spread":false},{"title":"PCB1PCBECO2018-11-2815-41-36.LOG <span style='color:#111;'>9.54KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2522-13-36.LOG <span style='color:#111;'>205B</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2516-17-20.LOG <span style='color:#111;'>234B</span>","children":null,"spread":false},{"title":"2018-9-20SCHECO2018-11-2815-41-23.LOG <span style='color:#111;'>2.88KB</span>","children":null,"spread":false},{"title":"2018-9-20PCBECO2018-9-2516-38-20.LOG <span style='color:#111;'>447B</span>","children":null,"spread":false}],"spread":false},{"title":"2018-9-20.PrjPcbStructure <span style='color:#111;'>51B</span>","children":null,"spread":false},{"title":"PcbLib1.PcbLib <span style='color:#111;'>38.00KB</span>","children":null,"spread":false},{"title":"2018-12-11.PcbDocPreview <span style='color:#111;'>39.40KB</span>","children":null,"spread":false},{"title":"2018-12-11.PcbDoc <span style='color:#111;'>1.33MB</span>","children":null,"spread":false},{"title":"PCB1.PcbDocPreview <span style='color:#111;'>4.45KB</span>","children":null,"spread":false},{"title":"2018-9-20.SchDocPreview <span style='color:#111;'>56.47KB</span>","children":null,"spread":false},{"title":"ProjectOutputsfor2018-9-20","children":[{"title":"DesignRuleCheck-2018-9-20.drc <span style='color:#111;'>13.22KB</span>","children":null,"spread":false},{"title":"DesignRuleCheck-2018-9-20.html <span style='color:#111;'>143.65KB</span>","children":null,"spread":false}],"spread":true},{"title":"Schlib1.SchLib <span style='color:#111;'>11.50KB</span>","children":null,"spread":false},{"title":"2018-9-20.SchDoc <span style='color:#111;'>212.00KB</span>","children":null,"spread":false},{"title":"PCB1.PcbDoc <span style='color:#111;'>80.50KB</span>","children":null,"spread":false}],"spread":false}],"spread":true}]