FFT64+FPGA+verilogHDL

[{"title":"（214个子文件657KB）FFT64+FPGA+verilogHDL","children":[{"title":"timing_violators.rpt <span style='color:#111;'>550B</span>","children":null,"spread":false},{"title":"design.rpt <span style='color:#111;'>999B</span>","children":null,"spread":false},{"title":"timing.rpt <span style='color:#111;'>17.79KB</span>","children":null,"spread":false},{"title":"power.rpt <span style='color:#111;'>1.11KB</span>","children":null,"spread":false},{"title":"area.rpt <span style='color:#111;'>634B</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]