[{"title":"(39个子文件473KB)XilinxSdram参考设计:含Verilog和VHDL版本级详细说明文档.7z","children":[{"title":"verilog","children":[{"title":"src","children":[{"title":"define.v <span style='color:#111;'>758B</span>","children":null,"spread":false},{"title":"rcd_cntr.v <span style='color:#111;'>1.30KB</span>","children":null,"spread":false},{"title":"sdrmc_state.v <span style='color:#111;'>6.01KB</span>","children":null,"spread":false},{"title":"cslt_cntr.v <span style='color:#111;'>1.30KB</span>","children":null,"spread":false},{"title":"ki_cntr.v <span style='color:#111;'>1.27KB</span>","children":null,"spread":false},{"title":"sdrm.v <span style='color:#111;'>13.59KB</span>","children":null,"spread":false},{"title":"sys_int.v <span style='color:#111;'>7.39KB</span>","children":null,"spread":false},{"title":"ref_cntr.v <span style='color:#111;'>1.39KB</span>","children":null,"spread":false},{"title":"brst_cntr.v <span style='color:#111;'>1.38KB</span>","children":null,"spread":false},{"title":"sdrm_t.v <span style='color:#111;'>5.00KB</span>","children":null,"spread":false}],"spread":true},{"title":"post_route","children":[{"title":"tb_post_route.v <span style='color:#111;'>7.85KB</span>","children":null,"spread":false},{"title":"post_route.vpd <span style='color:#111;'>753.69KB</span>","children":null,"spread":false},{"title":"string_decode_post_route.v <span style='color:#111;'>1.67KB</span>","children":null,"spread":false},{"title":"post_route.cfg <span style='color:#111;'>1.33KB</span>","children":null,"spread":false},{"title":"sdrm_par.sdf <span style='color:#111;'>696.62KB</span>","children":null,"spread":false},{"title":"post_route.log <span style='color:#111;'>41.22KB</span>","children":null,"spread":false},{"title":"sdrm_par.v <span style='color:#111;'>346.07KB</span>","children":null,"spread":false},{"title":"run_sim <span style='color:#111;'>310B</span>","children":null,"spread":false}],"spread":true},{"title":"par","children":[{"title":"sdrm.edf <span style='color:#111;'>318.92KB</span>","children":null,"spread":false},{"title":"sdrm_par.sdf <span style='color:#111;'>696.62KB</span>","children":null,"spread":false},{"title":"sdrm.ucf <span style='color:#111;'>5.04KB</span>","children":null,"spread":false},{"title":"sdrm_par.v <span style='color:#111;'>346.07KB</span>","children":null,"spread":false},{"title":"run_par <span style='color:#111;'>947B</span>","children":null,"spread":false}],"spread":true},{"title":"synth","children":[{"title":"sdrm.edf <span style='color:#111;'>318.92KB</span>","children":null,"spread":false},{"title":"sdrm.scr <span style='color:#111;'>3.16KB</span>","children":null,"spread":false},{"title":"setup.scr <span style='color:#111;'>3.16KB</span>","children":null,"spread":false},{"title":"run_synth <span style='color:#111;'>62B</span>","children":null,"spread":false}],"spread":true},{"title":"func_sim","children":[{"title":"tb_sdrm.v <span style='color:#111;'>7.92KB</span>","children":null,"spread":false},{"title":"func_sim.cfg <span style='color:#111;'>1.40KB</span>","children":null,"spread":false},{"title":"func_sim.log <span style='color:#111;'>48.36KB</span>","children":null,"spread":false},{"title":"string_decode_fn.v <span style='color:#111;'>5.61KB</span>","children":null,"spread":false},{"title":"run_sim <span style='color:#111;'>176B</span>","children":null,"spread":false},{"title":"func_sim.vpd <span style='color:#111;'>200.86KB</span>","children":null,"spread":false}],"spread":true},{"title":"micron","children":[{"title":"bank1.txt <span style='color:#111;'>200B</span>","children":null,"spread":false},{"title":"mt48lc1m16a1-8a.v <span style='color:#111;'>34.22KB</span>","children":null,"spread":false},{"title":"mt48lc1m16a1.v <span style='color:#111;'>35.42KB</span>","children":null,"spread":false},{"title":"bank0.txt <span style='color:#111;'>200B</span>","children":null,"spread":false},{"title":"test.v <span style='color:#111;'>31.88KB</span>","children":null,"spread":false}],"spread":true},{"title":"README <span style='color:#111;'>6.36KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}]