[{"title":"(42个子文件69.76MB)Vivado从此开始.zip","children":[{"title":"Vivado从此开始","children":[{"title":"Video_13_Create_Basic_Clock_Period_Constraint.pdf <span style='color:#111;'>1.16MB</span>","children":null,"spread":false},{"title":"Video_27_UltraFast_Design(5)_Defining_Clock_Groups.pdf <span style='color:#111;'>923.57KB</span>","children":null,"spread":false},{"title":"Video_39_TCL_Vivado_One_World_5.pdf <span style='color:#111;'>1.18MB</span>","children":null,"spread":false},{"title":"Video_22_UltraFast_Design(1)_Basic_Introduction.pdf <span style='color:#111;'>899.75KB</span>","children":null,"spread":false},{"title":"Video_33_UltraFast_Design(11)_Power_Est_Opt.pdf <span style='color:#111;'>789.81KB</span>","children":null,"spread":false},{"title":"Video_24_UltraFast_Design(3)_RTL_Coding(1).pdf <span style='color:#111;'>986.87KB</span>","children":null,"spread":false},{"title":"Video_34_Vivado_IP_Integrator.pdf <span style='color:#111;'>1.33MB</span>","children":null,"spread":false},{"title":"Video_25_UltraFast_Design(3)_RTL_Coding(2).pdf <span style='color:#111;'>1.51MB</span>","children":null,"spread":false},{"title":"Video_16_Virtual_Clock.pdf <span style='color:#111;'>1.12MB</span>","children":null,"spread":false},{"title":"Video_9_Debug.pdf <span style='color:#111;'>1.12MB</span>","children":null,"spread":false},{"title":"Video_12_Basic_Concept_and_Terminology_of_Timing_Analysis.pdf <span style='color:#111;'>974.22KB</span>","children":null,"spread":false},{"title":"Video_38_TCL_Vivado_One_World_4.pdf <span style='color:#111;'>635.34KB</span>","children":null,"spread":false},{"title":"Video_37_TCL_Vivado_One_World_3.pdf <span style='color:#111;'>948.97KB</span>","children":null,"spread":false},{"title":"Video_21_Design_Analysis_After_Synthesis_PartII.pdf <span style='color:#111;'>778.12KB</span>","children":null,"spread":false},{"title":"Video_10_IO_and_Clock_Planning.pdf <span style='color:#111;'>1.01MB</span>","children":null,"spread":false},{"title":"Video_31_UltraFast_Design(9)_Timing_Closure_Part1.pdf <span style='color:#111;'>684.91KB</span>","children":null,"spread":false},{"title":"Video_40_TCL_Vivado_One_World_6.pdf <span style='color:#111;'>1.22MB</span>","children":null,"spread":false},{"title":"Video_1_Vivado_Design_Flow_Overview.pdf <span style='color:#111;'>1.00MB</span>","children":null,"spread":false},{"title":"Video_8_Five_Most_Commonly_Used_Tcl_Commands.pdf <span style='color:#111;'>1.62MB</span>","children":null,"spread":false},{"title":"Video_5_Synthesis.pdf <span style='color:#111;'>1.28MB</span>","children":null,"spread":false},{"title":"Video_15_Setting_Output_Delay.pdf <span style='color:#111;'>1.12MB</span>","children":null,"spread":false},{"title":"Video_3_Logic_Simulation_with_XSim.pdf <span style='color:#111;'>784.84KB</span>","children":null,"spread":false},{"title":"Video_14_Setting_Input_Delay.pdf <span style='color:#111;'>1.09MB</span>","children":null,"spread":false},{"title":"Video_6_Implementation.pdf <span style='color:#111;'>1.19MB</span>","children":null,"spread":false},{"title":"Video_26_UltraFast_Design(4)_Timing_Constraint.pdf <span style='color:#111;'>1.24MB</span>","children":null,"spread":false},{"title":"Video_28_UltraFast_design(6)_Manage_IP_Constraints.pdf <span style='color:#111;'>558.10KB</span>","children":null,"spread":false},{"title":"Video_20_Design_Analysis_After_Synthesis_PartI.pdf <span style='color:#111;'>905.31KB</span>","children":null,"spread":false},{"title":"Video_4_Logic_Simulation_with_ModelSim.pdf <span style='color:#111;'>674.29KB</span>","children":null,"spread":false},{"title":"Video_18_Setting_False_Path.pdf <span style='color:#111;'>875.17KB</span>","children":null,"spread":false},{"title":"Video_29_UltraFast_Design(7)_Use_DRC_in_Vivado.pdf <span style='color:#111;'>761.96KB</span>","children":null,"spread":false},{"title":"Video_17_Setting_Multicycle_Path_Constraint.pdf <span style='color:#111;'>736.10KB</span>","children":null,"spread":false},{"title":"Video_30_UltraFast_Design(8)_Impl_Strategies.pdf <span style='color:#111;'>850.32KB</span>","children":null,"spread":false},{"title":"Video_41_TCL_Vivado_One_World_7.pdf <span style='color:#111;'>1.39MB</span>","children":null,"spread":false},{"title":"Video_7_Incremental_Implementation.pdf <span style='color:#111;'>987.08KB</span>","children":null,"spread":false},{"title":"Video_2_Designing_with_IP.pdf <span style='color:#111;'>1.13MB</span>","children":null,"spread":false},{"title":"Video_19_XDC_Precedence.pdf <span style='color:#111;'>1.05MB</span>","children":null,"spread":false},{"title":"Video_35_TCL_Vivado_One_World_1.pdf <span style='color:#111;'>1.21MB</span>","children":null,"spread":false},{"title":"Video_36_TCL_Vivado_One_World_2.pdf <span style='color:#111;'>1.31MB</span>","children":null,"spread":false},{"title":"Video_23_UltraFast_Design(2)_Clocking.pdf <span style='color:#111;'>1.28MB</span>","children":null,"spread":false},{"title":"Video_32_UltraFast_Design(10)_Timing_Closure_Part2.pdf <span style='color:#111;'>882.90KB</span>","children":null,"spread":false},{"title":"Video_11_Some_Tips_About_Design_Flow.pdf <span style='color:#111;'>1.26MB</span>","children":null,"spread":false}],"spread":false},{"title":"Vivado从此开始.pdf <span style='color:#111;'>42.63MB</span>","children":null,"spread":false}],"spread":true}]