MSP432用户手册

MSP432用户手册
MSP432低功耗高性能并存10.1DigitalI/OIntroductionThedigitalI/Ofeaturesinclude:•IndependentlyprogrammableindividualI/Os•Anycombinationofinputoroutput•Individuallyconfigurableinterruptsforports(availableforcertainportsonly)•Independentinputandoutputdataregisters•Individuallyconfigurablepulluporpulldownresistors•Wake-upcapabilityfromultra-lowpowermodes(availableforcertainportsonly)•IndividuallyconfigurablehighdriveI/Os(availableforcertainI/Osonly)DeviceswithinthefamilymayhaveuptoelevendigitalI/Oportsimplemented(P1toP10andPJ).MostportscontaineightI/Olines;however,someportsmaycontainless(seethedevice-specificdatasheetforportsavailable).EachI/Olineisindividuallyconfigurableforinputoroutputdirection,andeachcanbeindividuallyreadorwritten.EachI/Olineisindividuallyconfigurableforpulluporpulldownresistors.Certainportshaveinterruptandwake-upcapabilityfromultra-lowpowermodes(seedevicespecificdatasheetforportswithinterruptandwake-upcapability).Eachinterruptcanbeindividuallyenabledandconfiguredtoprovideaninterruptonarisingorfallingedgeofaninputsignal.AllinterruptsarefedintoanencodedInterruptVectorregister,allowingtheapplicationtodeterminewhichsub-pinofaporthasgeneratedtheevent.Individualportscanbeaccessedasbyte-wideportsorcanbecombinedintohalf-word-wideports.PortpairsP1andP2,P3andP4,P5andP6,P7andP8,andsoon,areassociatedwiththenamesPA,PB,PC,PD,andsoon,respectively.Allportregistersarehandledinthismannerwiththisnamingconvention.Themainexceptionaretheinterruptvectorregisters,forexample,interruptsforportsP1andP2mustbehandledthroughP1IVandP2IV,PAIVdoesnotexist.WhenwritingtoportPAwithhalf-wordoperations,all16bitsarewrittentotheport.WhenwritingtothelowerbyteofportPAusingbyteoperations, 本软件ID:8625303