[{"title":"(145个子文件4.16MB)基于VerilogHDL数字频率计的设计与实现","children":[{"title":"display.v <span style='color:#111;'>568B</span>","children":null,"spread":false},{"title":"frequency.qsf <span style='color:#111;'>24.70KB</span>","children":null,"spread":false},{"title":"frequency.done <span style='color:#111;'>26B</span>","children":null,"spread":false},{"title":"frequency.qsf.bak <span style='color:#111;'>4.87KB</span>","children":null,"spread":false},{"title":"frequency.sta.summary <span style='color:#111;'>4.70KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]