[{"title":"(13个子文件17.9MB)EDA技术与verilog王金明徐","children":[{"title":"EDA技术与Verilog设计第6章.ppt <span style='color:#111;'>201.50KB</span>","children":null,"spread":false},{"title":"EDA技术与Verilog设计王金明版第10章.ppt <span style='color:#111;'>1.18MB</span>","children":null,"spread":false},{"title":"第3章数字系统设计verilog-HDL(第6版)-王金明.pdf <span style='color:#111;'>3.61MB</span>","children":null,"spread":false},{"title":"EDA技术与Verilog设计第8章.ppt <span style='color:#111;'>564.00KB</span>","children":null,"spread":false},{"title":"EDA技术与Verilog设计第7章.ppt <span style='color:#111;'>251.00KB</span>","children":null,"spread":false},{"title":"第2章-EDA技术与Verilog设计.ppt <span style='color:#111;'>3.65MB</span>","children":null,"spread":false},{"title":"EDA技术与Verilog设计第3章.ppt <span style='color:#111;'>1.80MB</span>","children":null,"spread":false},{"title":"第7章数字系统设计verilog-HDL(第6版)王金明.pdf <span style='color:#111;'>4.11MB</span>","children":null,"spread":false},{"title":"数字系统设计与Verilog-HDL(第4版)[王金明]第1章.ppt <span style='color:#111;'>1.15MB</span>","children":null,"spread":false},{"title":"EDA技术与Verilog设计第4章.ppt <span style='color:#111;'>296.50KB</span>","children":null,"spread":false},{"title":"《EDA技术与Verilog设计》第7章:Verilog设计的层次与风格.ppt <span style='color:#111;'>248.50KB</span>","children":null,"spread":false},{"title":"第6章数字系统设计verilog-HDL(第6版)王金明.pdf <span style='color:#111;'>4.97MB</span>","children":null,"spread":false},{"title":"EDA技术与Verilog设计-第三章-Verilog设计初步.ppt <span style='color:#111;'>465.50KB</span>","children":null,"spread":false}],"spread":true}]