[{"title":"(5个子文件4KB)verilog实现pwm输出按键控制数码管显示频率和占空比","children":[{"title":"pwm","children":[{"title":"TOP.v <span style='color:#111;'>1.34KB</span>","children":null,"spread":false},{"title":"CTRL.v <span style='color:#111;'>4.07KB</span>","children":null,"spread":false},{"title":"KEY_SCAN.v <span style='color:#111;'>1.01KB</span>","children":null,"spread":false},{"title":"SMG.v <span style='color:#111;'>7.75KB</span>","children":null,"spread":false},{"title":"bin_bcd_f.v <span style='color:#111;'>3.65KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}]