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SOCVerilog源文件

上传者: qq_36484453 | 上传时间:2015/4/3 17:36:36 | 文件大小:63KB | 文件类型:zip
SOCVerilog源文件
基于MIPS指令集的32位五级流水线的CPU设计与Verilog实现。
该CPU可以实现28条基本指令。
基于SMIC0.25μm工艺库,使用DesignCompile与NCVerilog对设计分别进行逻辑综合和后仿,根据面积、时序等信息对设计进行了优化。
最初,为该CPU添加了共享总线,以及UART与GPIO接口,实现了一个简单的SoC,并编写了测试代码,在Modelsim上完成了功能仿真和时序仿真。

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