[{"title":"(48个子文件63KB)SOCVerilog源文件","children":[{"title":"SoC","children":[{"title":"IF_stage","children":[{"title":"cpu.h <span style='color:#111;'>1.53KB</span>","children":null,"spread":false},{"title":"bus.h <span style='color:#111;'>511B</span>","children":null,"spread":false},{"title":"if_stage_0tb.v <span style='color:#111;'>1.84KB</span>","children":null,"spread":false},{"title":"if_stage_0tb.v.bak <span style='color:#111;'>1.71KB</span>","children":null,"spread":false},{"title":"if_reg.v <span style='color:#111;'>1.50KB</span>","children":null,"spread":false},{"title":"if_stage.v <span style='color:#111;'>2.20KB</span>","children":null,"spread":false},{"title":"isa.h <span style='color:#111;'>1.33KB</span>","children":null,"spread":false},{"title":"work","children":[{"title":"bus_if","children":[{"title":"_primary.dat <span style='color:#111;'>3.14KB</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>1.23KB</span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'>1.02KB</span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'>19.30KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>2.78KB</span>","children":null,"spread":false}],"spread":true},{"title":"_vmake <span style='color:#111;'>26B</span>","children":null,"spread":false},{"title":"if_stage","children":[{"title":"_primary.dat <span style='color:#111;'>1.73KB</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>1.29KB</span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'>247B</span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'>11.57KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>2.26KB</span>","children":null,"spread":false}],"spread":true},{"title":"if_stage_0tb","children":[{"title":"_primary.dat <span style='color:#111;'>1.63KB</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>84B</span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'>1.58KB</span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'>14.72KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>1.94KB</span>","children":null,"spread":false}],"spread":true},{"title":"_temp","children":[{"title":"vlogbs5fka <span style='color:#111;'>1.33KB</span>","children":null,"spread":false},{"title":"vlog7cye07 <span style='color:#111;'>1.41KB</span>","children":null,"spread":false},{"title":"vlog27t4ew <span style='color:#111;'>1.25KB</span>","children":null,"spread":false},{"title":"vlog123grn <span style='color:#111;'>1.33KB</span>","children":null,"spread":false},{"title":"vlog43esen <span style='color:#111;'>1.46KB</span>","children":null,"spread":false},{"title":"vlog3e0m26 <span style='color:#111;'>1.34KB</span>","children":null,"spread":false},{"title":"vlogac28ri <span style='color:#111;'>1.29KB</span>","children":null,"spread":false},{"title":"vlogtvm0gf <span style='color:#111;'>1.25KB</span>","children":null,"spread":false}],"spread":false},{"title":"if_reg","children":[{"title":"_primary.dat <span style='color:#111;'>1.20KB</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>661B</span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'>364B</span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'>7.10KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>1.13KB</span>","children":null,"spread":false}],"spread":false},{"title":"_info <span style='color:#111;'>1.35KB</span>","children":null,"spread":false}],"spread":true},{"title":"if_stage.cr.mti <span style='color:#111;'>1.05KB</span>","children":null,"spread":false},{"title":"if_stage_tb.bak <span style='color:#111;'>1.57KB</span>","children":null,"spread":false},{"title":"nettype.h <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"if_stage_tb <span style='color:#111;'>1.85KB</span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'>64.00KB</span>","children":null,"spread":false},{"title":"stddef.h <span style='color:#111;'>522B</span>","children":null,"spread":false},{"title":"bus_if.v <span style='color:#111;'>4.67KB</span>","children":null,"spread":false},{"title":"global_config.h <span style='color:#111;'>329B</span>","children":null,"spread":false},{"title":"if_stage.v.bak <span style='color:#111;'>2.09KB</span>","children":null,"spread":false},{"title":"tcl_stacktrace.txt <span style='color:#111;'>644B</span>","children":null,"spread":false},{"title":"if_stage.mpf <span style='color:#111;'>78.42KB</span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}]