FPGA（UART），基于QUARTusII环境，verilog语言编写，

[{"title":"（135个子文件2.16MB）FPGA（UART），基于QUARTusII环境，verilog语言编写，","children":[{"title":"UART.tan.summary <span style='color:#111;'>1.73KB</span>","children":null,"spread":false},{"title":"UART.v.bak <span style='color:#111;'>567B</span>","children":null,"spread":false},{"title":"UART.vwf <span style='color:#111;'>17.63KB</span>","children":null,"spread":false},{"title":"UART.map.summary <span style='color:#111;'>453B</span>","children":null,"spread":false},{"title":"UART.map_bb.cdb <span style='color:#111;'>763B</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]