[{"title":"(71个子文件2.53MB)FPGA控制DM9000A进行以太网数据收发的Verilog实现","children":[{"title":"FPGA控制DM9000A进行以太网数据收发的Verilog实现","children":[{"title":"DM9000A.H <span style='color:#111;'>3.63KB</span>","children":null,"spread":false},{"title":"Dm9000a","children":[{"title":"Dm9000a_IORD.v <span style='color:#111;'>3.09KB</span>","children":null,"spread":false},{"title":"Dm9000a_Iow.v <span style='color:#111;'>4.19KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.v <span style='color:#111;'>38.45KB</span>","children":null,"spread":false},{"title":"Dm9000a_IOWR.v <span style='color:#111;'>3.18KB</span>","children":null,"spread":false},{"title":"Dm9000a_Ior.v <span style='color:#111;'>5.56KB</span>","children":null,"spread":false},{"title":"Dm9000a.def <span style='color:#111;'>2.96KB</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>160B</span>","children":null,"spread":false},{"title":"phy_write.v <span style='color:#111;'>10.09KB</span>","children":null,"spread":false},{"title":"Dm9000a_IO.v <span style='color:#111;'>2.26KB</span>","children":null,"spread":false}],"spread":true},{"title":"Test","children":[{"title":"Dm9000a_IOWR","children":[{"title":"Dm9000a_IOWR_Test.v <span style='color:#111;'>2.96KB</span>","children":null,"spread":false},{"title":"Dm9000a_IOWR_Test.qpf <span style='color:#111;'>920B</span>","children":null,"spread":false},{"title":"Dm9000a_IOWR_Test.vwf <span style='color:#111;'>20.55KB</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>96B</span>","children":null,"spread":false},{"title":"Dm9000a_IOWR_Test.qsf <span style='color:#111;'>2.95KB</span>","children":null,"spread":false}],"spread":true},{"title":"Dm9000a_IO","children":[{"title":"Dm9000a_IO.qsf <span style='color:#111;'>3.64KB</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>80B</span>","children":null,"spread":false},{"title":"Dm9000a_IO_Test.v <span style='color:#111;'>1.09KB</span>","children":null,"spread":false},{"title":"Dm9000a_IO.qpf <span style='color:#111;'>913B</span>","children":null,"spread":false}],"spread":true},{"title":"Dm9000a_IORD","children":[{"title":"Dm9000a_IORD_Test.v <span style='color:#111;'>2.57KB</span>","children":null,"spread":false},{"title":"Dm9000a_IORD_Test.vwf <span style='color:#111;'>18.90KB</span>","children":null,"spread":false},{"title":"Dm9000a_IORD_Test.qsf <span style='color:#111;'>2.74KB</span>","children":null,"spread":false},{"title":"Dm9000a_IORD_Test.qpf <span style='color:#111;'>920B</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>96B</span>","children":null,"spread":false}],"spread":true},{"title":"Dm9000a_Ior","children":[{"title":"Dm9000a_Ior.qpf <span style='color:#111;'>914B</span>","children":null,"spread":false},{"title":"Dm9000a_Ior.qsf <span style='color:#111;'>2.42KB</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>96B</span>","children":null,"spread":false},{"title":"Dm9000a_Ior.qws <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"Dm9000a_Ior.vwf <span style='color:#111;'>35.78KB</span>","children":null,"spread":false}],"spread":true},{"title":"Dm9000a_Init","children":[{"title":"Dm9000a_Init.qpf <span style='color:#111;'>915B</span>","children":null,"spread":false},{"title":"Dm9000a_Init.map.rpt <span style='color:#111;'>25.87KB</span>","children":null,"spread":false},{"title":"db","children":[{"title":"Dm9000a_Init.db_info <span style='color:#111;'>136B</span>","children":null,"spread":false}],"spread":true},{"title":"Dm9000a_Init.flow.rpt <span style='color:#111;'>5.50KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.pin <span style='color:#111;'>30.50KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.vwf <span style='color:#111;'>87.97KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.qsf <span style='color:#111;'>4.51KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.done <span style='color:#111;'>26B</span>","children":null,"spread":false},{"title":"Dm9000a_Init.fit.summary <span style='color:#111;'>618B</span>","children":null,"spread":false},{"title":"Dm9000a_Init.tan.summary <span style='color:#111;'>3.57KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.fit.rpt <span style='color:#111;'>126.15KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.sof <span style='color:#111;'>464.56KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.tan.rpt <span style='color:#111;'>257.82KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.qws <span style='color:#111;'>587B</span>","children":null,"spread":false},{"title":"Dm9000a_Init.fit.smsg <span style='color:#111;'>513B</span>","children":null,"spread":false},{"title":"Dm9000a_Init.map.summary <span style='color:#111;'>475B</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>336B</span>","children":null,"spread":false},{"title":"Dm9000a_Init.asm.rpt <span style='color:#111;'>8.37KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.pof <span style='color:#111;'>2.00MB</span>","children":null,"spread":false},{"title":"Dm9000a_Init_Test.v <span style='color:#111;'>15.59KB</span>","children":null,"spread":false},{"title":"Dm9000a_Init.map.smsg <span style='color:#111;'>93B</span>","children":null,"spread":false}],"spread":false},{"title":"Dm9000a_Iow","children":[{"title":"Dm9000a_Iow.vwf <span style='color:#111;'>26.03KB</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>96B</span>","children":null,"spread":false},{"title":"Dm9000a_Iow.qpf <span style='color:#111;'>914B</span>","children":null,"spread":false},{"title":"Dm9000a_Iow.qsf <span style='color:#111;'>2.42KB</span>","children":null,"spread":false},{"title":"Dm9000a_Iow.qws <span style='color:#111;'>90B</span>","children":null,"spread":false}],"spread":true},{"title":"vssver.scc <span style='color:#111;'>48B</span>","children":null,"spread":false},{"title":"Dm9000a_WriteRead","children":[{"title":"Dm9000a_WriteRead.qpf <span style='color:#111;'>920B</span>","children":null,"spread":false},{"title":"Dm9000a_WriteRead.v <span style='color:#111;'>19.86KB</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>112B</span>","children":null,"spread":false},{"title":"Dm9000a_WriteRead.vwf <span style='color:#111;'>24.20KB</span>","children":null,"spread":false},{"title":"Dm9000a_WriteRead.qws <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"Dm9000a_WriteRead.qsf <span style='color:#111;'>4.36KB</span>","children":null,"spread":false}],"spread":true},{"title":"phy_write","children":[{"title":"phy_write.qsf <span style='color:#111;'>2.41KB</span>","children":null,"spread":false},{"title":"phy_write.vwf <span style='color:#111;'>53.14KB</span>","children":null,"spread":false},{"title":"phy_write.qws <span style='color:#111;'>90B</span>","children":null,"spread":false},{"title":"vssver.scc <span style='color:#111;'>96B</span>","children":null,"spread":false},{"title":"phy_write.qpf <span style='color:#111;'>912B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"DM9000A.pdf <span style='color:#111;'>1.68MB</span>","children":null,"spread":false},{"title":"FPGA控制DM9000A进行以太网数据收发的Verilog实现-恋恋风尘.mht <span style='color:#111;'>431.33KB</span>","children":null,"spread":false},{"title":"Dm9000a和FPGA的接口全图.jpg <span style='color:#111;'>1.42MB</span>","children":null,"spread":false},{"title":"DM9000A.C <span style='color:#111;'>9.21KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}]