ddr4fpgaxilinx仿真模型

[{"title":"（18个子文件366KB）ddr4fpgaxilinx仿真模型","children":[{"title":"ddr4_rdimm_wrapper","children":[{"title":"ddr4_dir_detect.sv <span style='color:#111;'>854B</span>","children":null,"spread":false},{"title":"ddr4_bi_delay.sv <span style='color:#111;'>5.11KB</span>","children":null,"spread":false},{"title":"ddr4_db_delay_model.sv <span style='color:#111;'>4.20KB</span>","children":null,"spread":false},{"title":"ddr4_rank.sv <span style='color:#111;'>21.74KB</span>","children":null,"spread":false},{"title":"ddr4_rdimm_wrapper.sv <span style='color:#111;'>20.16KB</span>","children":null,"spread":false},{"title":"ddr4_rcd_model.sv <span style='color:#111;'>6.91KB</span>","children":null,"spread":false},{"title":"ddr4_dimm.sv <span style='color:#111;'>26.36KB</span>","children":null,"spread":false},{"title":"ddr4_db_dly_dir.sv <span style='color:#111;'>4.56KB</span>","children":null,"spread":false}],"spread":true},{"title":"ddr4_model","children":[{"title":"arch_package.sv <span style='color:#111;'>53.34KB</span>","children":null,"spread":false},{"title":"MemoryArray.sv <span style='color:#111;'>22.92KB</span>","children":null,"spread":false},{"title":"arch_defines.v <span style='color:#111;'>865B</span>","children":null,"spread":false},{"title":"ddr4_sdram_model_wrapper.sv <span style='color:#111;'>3.13KB</span>","children":null,"spread":false},{"title":"StateTableCore.sv <span style='color:#111;'>203.28KB</span>","children":null,"spread":false},{"title":"timing_tasks.sv <span style='color:#111;'>22.20KB</span>","children":null,"spread":false},{"title":"StateTable.sv <span style='color:#111;'>7.13KB</span>","children":null,"spread":false},{"title":"proj_package.sv <span style='color:#111;'>17.73KB</span>","children":null,"spread":false},{"title":"interface.sv <span style='color:#111;'>966B</span>","children":null,"spread":false},{"title":"ddr4_model.sv <span style='color:#111;'>182.32KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}]