[{"title":"(56个子文件107KB)7-VerilogHDL二分频与三分频设计.7z","children":[{"title":"7-VerilogHDL二分频与三分频设计","children":[{"title":"vivado","children":[{"title":"7_design_top","children":[{"title":"design_top","children":[{"title":"design_top.srcs","children":[{"title":"sources_1","children":[{"title":"new","children":[{"title":"divider3_top.v <span style='color:#111;'>716B</span>","children":null,"spread":false},{"title":"divider2_top.v <span style='color:#111;'>247B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"sim_1","children":[{"title":"new","children":[{"title":"top_tb.v <span style='color:#111;'>317B</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"design_top.cache","children":[{"title":"wt","children":[{"title":"webtalk_pa.xml <span style='color:#111;'>4.20KB</span>","children":null,"spread":false},{"title":"project.wpc <span style='color:#111;'>61B</span>","children":null,"spread":false},{"title":"gui_handlers.wdf <span style='color:#111;'>3.77KB</span>","children":null,"spread":false},{"title":"java_command_handlers.wdf <span style='color:#111;'>1.11KB</span>","children":null,"spread":false},{"title":"xsim.wdf <span style='color:#111;'>239B</span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"design_top.xpr <span style='color:#111;'>10.78KB</span>","children":null,"spread":false},{"title":"design_top.sim","children":[{"title":"sim_1","children":[{"title":"behav","children":[{"title":"xsim","children":[{"title":"webtalk_23084.backup.jou <span style='color:#111;'>992B</span>","children":null,"spread":false},{"title":"top_tb_behav.wdb <span style='color:#111;'>13.38KB</span>","children":null,"spread":false},{"title":"xsim.dir","children":[{"title":"top_tb_behav","children":[{"title":"xsimcrash.log <span style='color:#111;'>144B</span>","children":null,"spread":false},{"title":"TempBreakPointFile.txt <span style='color:#111;'>29B</span>","children":null,"spread":false},{"title":"xsim.dbg <span style='color:#111;'>6.80KB</span>","children":null,"spread":false},{"title":"xsim.xdbg <span style='color:#111;'>984B</span>","children":null,"spread":false},{"title":"obj","children":[{"title":"xsim_1.win64.obj <span style='color:#111;'>3.23KB</span>","children":null,"spread":false},{"title":"xsim_0.win64.obj <span style='color:#111;'>7.85KB</span>","children":null,"spread":false},{"title":"xsim_1.c <span style='color:#111;'>5.01KB</span>","children":null,"spread":false}],"spread":false},{"title":"xsimk.exe <span style='color:#111;'>68.37KB</span>","children":null,"spread":false},{"title":"xsimkernel.log <span style='color:#111;'>321B</span>","children":null,"spread":false},{"title":"xsim.type <span style='color:#111;'>24B</span>","children":null,"spread":false},{"title":"xsim.mem <span style='color:#111;'>3.30KB</span>","children":null,"spread":false},{"title":"xsim.rtti <span style='color:#111;'>190B</span>","children":null,"spread":false},{"title":"xsimSettings.ini <span style='color:#111;'>1.41KB</span>","children":null,"spread":false},{"title":"webtalk","children":[{"title":"xsim_webtalk.tcl <span style='color:#111;'>3.70KB</span>","children":null,"spread":false},{"title":"usage_statistics_ext_xsim.html <span style='color:#111;'>3.23KB</span>","children":null,"spread":false},{"title":"usage_statistics_ext_xsim.wdm <span style='color:#111;'>1.09KB</span>","children":null,"spread":false},{"title":"usage_statistics_ext_xsim.xml <span style='color:#111;'>2.84KB</span>","children":null,"spread":false},{"title":".xsim_webtallk.info <span style='color:#111;'>64B</span>","children":null,"spread":false}],"spread":false},{"title":"Compile_Options.txt <span style='color:#111;'>246B</span>","children":null,"spread":false},{"title":"xsim.svtype <span style='color:#111;'>39B</span>","children":null,"spread":false},{"title":"xsim.reloc <span style='color:#111;'>1.28KB</span>","children":null,"spread":false},{"title":"xsim.rlx <span style='color:#111;'>791B</span>","children":null,"spread":false}],"spread":false},{"title":"xil_defaultlib","children":[{"title":"divider2_top.sdb <span style='color:#111;'>813B</span>","children":null,"spread":false},{"title":"xil_defaultlib.rlx <span style='color:#111;'>770B</span>","children":null,"spread":false},{"title":"top_tb.sdb <span style='color:#111;'>1.11KB</span>","children":null,"spread":false},{"title":"glbl.sdb <span style='color:#111;'>3.64KB</span>","children":null,"spread":false},{"title":"divider3_top.sdb <span style='color:#111;'>1.79KB</span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"xvlog.log <span style='color:#111;'>656B</span>","children":null,"spread":false},{"title":"xvlog.pb <span style='color:#111;'>1.07KB</span>","children":null,"spread":false},{"title":"webtalk.jou <span style='color:#111;'>992B</span>","children":null,"spread":false},{"title":"simulate.bat <span style='color:#111;'>900B</span>","children":null,"spread":false},{"title":"xsim.ini <span style='color:#111;'>40B</span>","children":null,"spread":false},{"title":"elaborate.bat <span style='color:#111;'>1.12KB</span>","children":null,"spread":false},{"title":"glbl.v <span style='color:#111;'>1.44KB</span>","children":null,"spread":false},{"title":"webtalk_23084.backup.log <span style='color:#111;'>1.14KB</span>","children":null,"spread":false},{"title":"elaborate.log <span style='color:#111;'>793B</span>","children":null,"spread":false},{"title":"top_tb_vlog.prj <span style='color:#111;'>354B</span>","children":null,"spread":false},{"title":"simulate.log <span style='color:#111;'>50B</span>","children":null,"spread":false},{"title":"xelab.pb <span style='color:#111;'>1.61KB</span>","children":null,"spread":false},{"title":"top_tb.tcl <span style='color:#111;'>460B</span>","children":null,"spread":false},{"title":".Xil","children":[{"title":"Webtalk-23084-XA-TSDN034","children":[{"title":"webtalk","children":null,"spread":false}],"spread":false},{"title":"Webtalk-15416-XA-TSDN034","children":[{"title":"webtalk","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"webtalk.log <span style='color:#111;'>1.14KB</span>","children":null,"spread":false},{"title":"compile.bat <span style='color:#111;'>830B</span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"design_top.hw","children":[{"title":"design_top.lpr <span style='color:#111;'>290B</span>","children":null,"spread":false}],"spread":true},{"title":"design_top.ip_user_files","children":[{"title":"README.txt <span style='color:#111;'>130B</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true},{"title":"fpga","children":[{"title":"7-VerilogHDL二分频与三分频设计.pdf <span style='color:#111;'>91.27KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]