[{"title":"(15个子文件42KB)ad7276verilog","children":[{"title":"ad706_7276","children":[{"title":"vsim.wlf <span style='color:#111;'>48.00KB</span>","children":null,"spread":false},{"title":"adg732_7276.mpf <span style='color:#111;'>30.26KB</span>","children":null,"spread":false},{"title":"ad706_7276.v <span style='color:#111;'>8.79KB</span>","children":null,"spread":false},{"title":"work","children":[{"title":"ad7276","children":[{"title":"verilog.asm <span style='color:#111;'>45.62KB</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>2.62KB</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>7.60KB</span>","children":null,"spread":false}],"spread":true},{"title":"_temp","children":null,"spread":false},{"title":"top2","children":[{"title":"verilog.asm <span style='color:#111;'>15.41KB</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>68B</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>2.21KB</span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'>417B</span>","children":null,"spread":false}],"spread":true},{"title":"adg732_7276.cr.mti <span style='color:#111;'>465B</span>","children":null,"spread":false},{"title":"ad706_7276.v.bak <span style='color:#111;'>8.79KB</span>","children":null,"spread":false},{"title":"top2.v <span style='color:#111;'>2.09KB</span>","children":null,"spread":false},{"title":"top2.v.bak <span style='color:#111;'>2.09KB</span>","children":null,"spread":false},{"title":"transcript <span style='color:#111;'>389B</span>","children":null,"spread":false}],"spread":true}],"spread":true}]