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Verilog计数器

上传者: expren0 | 上传时间:2025/4/22 12:32:18 | 文件大小:310KB | 文件类型:rar
Verilog计数器
此计数器是999,用数码管实现,包括分频模块,从20M分到1HZ,计数模块,动态扫描,显示译码等,完全可以在硬件上实现,只要改一下数,即可完成任意计数器 本软件ID:342959

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评论信息

  • 七夜子风:
    一般般吧,很普通2014-10-13
  • superYlcy:
    不错的思路。刚好期中考试考到了!相当感谢!2014-07-02
  • lyzpokemon:
    无工程文件,需要单个单个查看,但是思路借鉴了2014-03-02
  • mamazi530:
    对于初学者来说不是很好程序结构不明朗不容易看懂2013-08-19
  • 唔系圈圈:
    有好的地方,也有不好的2012-12-04

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