基于pllverilog写的倍频器

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style='color:#111;'>5.88KB</span>","children":null,"spread":false},{"title":"simulation","children":[{"title":"modelsim","children":[{"title":"pwm_modelsim.xrf <span style='color:#111;'>1.01KB</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak4 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"modelsim.ini <span style='color:#111;'>10.82KB</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak10 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak3 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak5 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"rtl_work","children":[{"title":"_vmake <span style='color:#111;'>26B</span>","children":null,"spread":false},{"title":"pwm_vlg_tst","children":[{"title":"verilog.prw <span style='color:#111;'>1.65KB</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>459B</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>82B</span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'>5.06KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>788B</span>","children":null,"spread":false}],"spread":false},{"title":"pll","children":[{"title":"verilog.prw <span style='color:#111;'>9.63KB</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>3.35KB</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>254B</span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'>28.12KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>2.69KB</span>","children":null,"spread":false}],"spread":false},{"title":"_temp","children":null,"spread":false},{"title":"pwm","children":[{"title":"verilog.prw <span style='color:#111;'>1.09KB</span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'>261B</span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'>254B</span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'>2.79KB</span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'>570B</span>","children":null,"spread":false}],"spread":false},{"title":"_info <span style='color:#111;'>747B</span>","children":null,"spread":false}],"spread":false},{"title":"pwm.vt.bak <span style='color:#111;'>2.98KB</span>","children":null,"spread":false},{"title":"pll.qip <span style='color:#111;'>0B</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak9 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak8 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm_v.sdo <span style='color:#111;'>2.99KB</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak11 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"greybox_tmp","children":[{"title":"cbx_args.txt <span style='color:#111;'>1.41KB</span>","children":null,"spread":false}],"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak2 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak1 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"msim_transcript <span style='color:#111;'>3.62KB</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak6 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm.vt <span style='color:#111;'>2.65KB</span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'>64.00KB</span>","children":null,"spread":false},{"title":"pwm_run_msim_rtl_verilog.do.bak7 <span style='color:#111;'>528B</span>","children":null,"spread":false},{"title":"pwm.vo <span style='color:#111;'>10.22KB</span>","children":null,"spread":false},{"title":"pwm.sft <span style='color:#111;'>108B</span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"pwm.qws <span style='color:#111;'>527B</span>","children":null,"spread":false},{"title":"pll.ppf <span style='color:#111;'>470B</span>","children":null,"spread":false},{"title":"pll.qip <span style='color:#111;'>436B</span>","children":null,"spread":false},{"title":"pwm.pof <span style='color:#111;'>512.20KB</span>","children":null,"spread":false},{"title":"pwm.dpf <span style='color:#111;'>239B</span>","children":null,"spread":false},{"title":"pwm.fit.smsg <span style='color:#111;'>513B</span>","children":null,"spread":false},{"title":"incremental_db","children":[{"title":"compiled_partitions","children":[{"title":"pwm.root_partition.cmp.dfp <span style='color:#111;'>33B</span>","children":null,"spread":false},{"title":"pwm.root_partition.map.cdb <span style='color:#111;'>1.42KB</span>","children":null,"spread":false},{"title":"pwm.db_info <span style='color:#111;'>153B</span>","children":null,"spread":false},{"title":"pwm.root_partition.map.dpi <span style='color:#111;'>3.16KB</span>","children":null,"spread":false},{"title":"pwm.root_partition.cmp.cdb <span style='color:#111;'>1.72KB</span>","children":null,"spread":false},{"title":"pwm.root_partition.cmp.kpt <span style='color:#111;'>208B</span>","children":null,"spread":false},{"title":"pwm.root_partition.hbdb.cdb <span style='color:#111;'>879B</span>","children":null,"spread":false},{"title":"pwm.root_partition.cmp.hdb <span style='color:#111;'>9.74KB</span>","children":null,"spread":false},{"title":"pwm.root_partition.map.hdb <span style='color:#111;'>9.57KB</span>","children":null,"spread":false},{"title":"pwm.root_partition.map.kpt <span style='color:#111;'>213B</span>","children":null,"spread":false},{"title":"pwm.root_partition.cmp.re.rcfdb <span style='color:#111;'>974B</span>","children":null,"spread":false},{"title":"pwm.root_partition.cmp.logdb <span style='color:#111;'>4B</span>","children":null,"spread":false},{"title":"pwm.root_partition.cmp.rcfdb <span style='color:#111;'>959B</span>","children":null,"spread":false}],"spread":false},{"title":"README <span style='color:#111;'>653B</span>","children":null,"spread":false}],"spread":true},{"title":"pwm_nativelink_simulation.rpt <span style='color:#111;'>1007B</span>","children":null,"spread":false},{"title":"pwm.fit.rpt <span style='color:#111;'>79.13KB</span>","children":null,"spread":false},{"title":"pwm.v <span style='color:#111;'>187B</span>","children":null,"spread":false},{"title":"pwm.map.summary <span style='color:#111;'>449B</span>","children":null,"spread":false},{"title":"greybox_tmp","children":[{"title":"cbx_args.txt <span style='color:#111;'>1.41KB</span>","children":null,"spread":false}],"spread":false},{"title":"pwm.bsf <span style='color:#111;'>1.90KB</span>","children":null,"spread":false},{"title":"pwm.done <span style='color:#111;'>26B</span>","children":null,"spread":false},{"title":"pwm.sof <span style='color:#111;'>147.53KB</span>","children":null,"spread":false},{"title":"pwm.qsf <span style='color:#111;'>3.66KB</span>","children":null,"spread":false},{"title":"pll_inst.v <span style='color:#111;'>116B</span>","children":null,"spread":false},{"title":"pwm.tan.summary <span style='color:#111;'>749B</span>","children":null,"spread":false},{"title":"pwm.tan.rpt <span style='color:#111;'>12.84KB</span>","children":null,"spread":false},{"title":"pll_bb.v <span style='color:#111;'>11.19KB</span>","children":null,"spread":false},{"title":"pwm.map.rpt <span style='color:#111;'>58.02KB</span>","children":null,"spread":false},{"title":"pwm.qpf <span style='color:#111;'>1.25KB</span>","children":null,"spread":false},{"title":"pwm.asm.rpt <span style='color:#111;'>6.86KB</span>","children":null,"spread":false},{"title":"pwm.flow.rpt <span style='color:#111;'>8.32KB</span>","children":null,"spread":false},{"title":"pll.v <span style='color:#111;'>14.96KB</span>","children":null,"spread":false}],"spread":false}],"spread":true}]