FPGAverilog例程+详细的注释

[{"title":"（2196个子文件18.25MB）FPGAverilog例程+详细的注释","children":[{"title":"luojiyi_demo.done <span style='color:#111;'>26B</span>","children":null,"spread":false},{"title":"luojiyi_demo.pof <span style='color:#111;'>128.18KB</span>","children":null,"spread":false},{"title":"topdesign.v.bak <span style='color:#111;'>7.30KB</span>","children":null,"spread":false},{"title":"luojiyi_demo.pre_map.hdb <span style='color:#111;'>17.77KB</span>","children":null,"spread":false},{"title":"luojiyi_demo.(4).cnf.cdb <span style='color:#111;'>1.93KB</span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":" <span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]