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FPGAUDP千兆以太网工程

上传者: chat1 | 上传时间:2024/5/9 1:21:54 | 文件大小:52KB | 文件类型:zip
FPGAUDP千兆以太网工程
基于FPGA的UDP硬件协议栈,全部用SystemVerilog写的,不需CPU参与,包括独立的MAC模块。
支持外部phy的配置,支持GMII和RGMII模式。
以下是接口inputclk50,inputrst_n,interfacetousermoduleinput[7:0]wr_data,inputwr_clk,inputwr_en,outputwr_full,output[7:0]rd_data,inputrd_clk,inputrd_en,outputrd_empty,input[31:0]local_ipaddr,//FPGAipaddressinput[31:0]remote_ipaddr,//PCipaddressinput[15:0]local_port,//FPGAportnumber//interfacetoethernetphyoutputmdc,inoutmdio,outputphy_rst_n,outputis_link_up,`ifdefRGMII_IFinput[3:0]rx_data,outputlogic[3:0]tx_data,`elseinput[7:0]rx_data,outputlogic[7:0]tx_data,`endifinputrx_clk,inputrx_data_valid,inputgtx_clk,outputlogictx_en

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评论信息

  • yongruishining:
    代码不错,很好2019-08-21
  • jkier:
    代码不错,非常牛。2018-07-06
  • pozhijiaoyou84739:
    看了代码,应该是上传者的原创,非常牛。2016-04-09

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