浙江理工大学数字电路实验实验七-时序逻辑电路的设计multisim电路模仿

[{"title":"（4个子文件328KB）浙江理工大学数字电路实验实验七-时序逻辑电路的设计multisim电路模拟","children":[{"title":"实验七-时序逻辑电路的设计","children":[{"title":"D触发器逻辑功能测试1.ms14 <span style='color:#111;'>90.30KB</span>","children":null,"spread":false},{"title":"D触发器逻辑功能测试3.ms14 <span style='color:#111;'>67.06KB</span>","children":null,"spread":false},{"title":"D触发器逻辑功能测试2.ms14 <span style='color:#111;'>116.17KB</span>","children":null,"spread":false},{"title":"利用74LS161设计BCD5421码十进制计数器.ms14 <span style='color:#111;'>91.75KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}]