verilog_AD9945_TCD1209

[{"title":"（12个子文件196KB）verilog_AD9945_TCD1209","children":[{"title":"AD9945_TCD1209","children":[{"title":"AD9945_TB.v <span style='color:#111;'>1.04KB</span>","children":null,"spread":false},{"title":"tcd1209.v <span style='color:#111;'>2.52KB</span>","children":null,"spread":false},{"title":"divide_10.v <span style='color:#111;'>413B</span>","children":null,"spread":false},{"title":"config.v <span style='color:#111;'>1.11KB</span>","children":null,"spread":false},{"title":"ad_data.v <span style='color:#111;'>1.00KB</span>","children":null,"spread":false},{"title":"altera_mf.v <span style='color:#111;'>2.10MB</span>","children":null,"spread":false},{"title":"PLL_bb.v <span style='color:#111;'>11.73KB</span>","children":null,"spread":false},{"title":"PLL2_bb.v <span style='color:#111;'>10.58KB</span>","children":null,"spread":false},{"title":"PLL.v <span style='color:#111;'>15.53KB</span>","children":null,"spread":false},{"title":"ad_config.v <span style='color:#111;'>1.07KB</span>","children":null,"spread":false},{"title":"PLL2.v <span style='color:#111;'>14.16KB</span>","children":null,"spread":false},{"title":"ad9945.v <span style='color:#111;'>1.01KB</span>","children":null,"spread":false}],"spread":false}],"spread":true}]