iMX6RexIMX6Q核心板CORTEX-A9四核DDR3ALTIUMAD设计硬件原理图+PCB+BOM文件.zip

[{"title":"（65个子文件20.5MB）iMX6RexIMX6Q核心板CORTEX-A9四核DDR3ALTIUMAD设计硬件原理图+PCB+BOM文件.zip","children":[{"title":"iMX6RexIMX6Q核心板DDR3ALTIUMAD设计原理图+PCB（12层）+BOM文件","children":[{"title":"iMX6RexModule_V1I1-2013DDR3lengthcalculator.xls <span style='color:#111;'>1007.00KB</span>","children":null,"spread":false},{"title":"iMX6RexModule_V1I1-2013-Schematic.pdf <span style='color:#111;'>6.80MB</span>","children":null,"spread":false},{"title":"Altium-Designerddr3设计技巧","children":[{"title":"用Altium-Designer实现DDR2的等长布线.doc <span style='color:#111;'>651.00KB</span>","children":null,"spread":false},{"title":"如何在AltiumDesigner中实现两片DDR等长走线.doc <span style='color:#111;'>1.64MB</span>","children":null,"spread":false},{"title":"Altium-Designer-DDR分支等长设置方法.pdf <span style='color:#111;'>1.48MB</span>","children":null,"spread":false},{"title":"Altium-Designer-蛇形等长布线和如何查看NET总长度.pdf <span style='color:#111;'>271.19KB</span>","children":null,"spread":false},{"title":"DDR布局布线规则与实例.pdf <span style='color:#111;'>4.21MB</span>","children":null,"spread":false}],"spread":true},{"title":"iMX6RexModule_V1I1ProjectFilessavedinAD2013","children":[{"title":"[08]-CPU-SPI,I2C,SD,MMC.SchDoc <span style='color:#111;'>880.00KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1_PCB.PcbDoc.htm <span style='color:#111;'>8.68KB</span>","children":null,"spread":false},{"title":"[19]-DOCREVISIONHISTORY.SchDoc <span style='color:#111;'>16.00KB</span>","children":null,"spread":false},{"title":"[01]-COVERPAGE.SchDocPreview <span style='color:#111;'>107.33KB</span>","children":null,"spread":false},{"title":"[17]-MECH.SchDocPreview <span style='color:#111;'>76.92KB</span>","children":null,"spread":false},{"title":"[14]-SPIFLASH,LEDS.SchDocPreview <span style='color:#111;'>35.56KB</span>","children":null,"spread":false},{"title":"[06]-CPU-HDMI,LVDS.SchDoc <span style='color:#111;'>693.50KB</span>","children":null,"spread":false},{"title":"[13]-ETHERNETPHY.SchDoc <span style='color:#111;'>598.50KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1.PrjPcb <span style='color:#111;'>71.23KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1_PCB.PcbDocPreview <span style='color:#111;'>90.77KB</span>","children":null,"spread":false},{"title":"license.txt <span style='color:#111;'>16.98KB</span>","children":null,"spread":false},{"title":"[13]-ETHERNETPHY.SchDocPreview <span style='color:#111;'>94.44KB</span>","children":null,"spread":false},{"title":"[05]-CPU-PCIE,SATA.SchDocPreview <span style='color:#111;'>61.30KB</span>","children":null,"spread":false},{"title":"StatusReport.Txt <span style='color:#111;'>417B</span>","children":null,"spread":false},{"title":"[14]-SPIFLASH,LEDS.SchDoc <span style='color:#111;'>120.00KB</span>","children":null,"spread":false},{"title":"[06]-CPU-HDMI,LVDS.SchDocPreview <span style='color:#111;'>81.22KB</span>","children":null,"spread":false},{"title":"[07]-CPU-USB,ETHERNET.SchDoc <span style='color:#111;'>562.50KB</span>","children":null,"spread":false},{"title":"[05]-CPU-PCIE,SATA.SchDoc <span style='color:#111;'>722.00KB</span>","children":null,"spread":false},{"title":"[04]-CPU-DDR3,DDR3MEM.SchDocPreview <span style='color:#111;'>197.33KB</span>","children":null,"spread":false},{"title":"[04]-CPU-DDR3,DDR3MEM.SchDoc <span style='color:#111;'>1.16MB</span>","children":null,"spread":false},{"title":"[02]-BLOCKDIAGRAM.SchDocPreview <span style='color:#111;'>75.75KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1Project.SchDocPreview <span style='color:#111;'>81.95KB</span>","children":null,"spread":false},{"title":"[03]-CONNECTORS.SchDoc <span style='color:#111;'>186.50KB</span>","children":null,"spread":false},{"title":"[19]-DOCREVISIONHISTORY.SchDocPreview <span style='color:#111;'>59.67KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1Project.SchDoc <span style='color:#111;'>25.50KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1.Dat <span style='color:#111;'>16.07KB</span>","children":null,"spread":false},{"title":"[02]-BLOCKDIAGRAM.SchDoc <span style='color:#111;'>25.00KB</span>","children":null,"spread":false},{"title":"iMX6RexModule_V1I1_3D.pdf <span style='color:#111;'>3.62MB</span>","children":null,"spread":false},{"title":"[09]-CPU-UART,AUDIO.SchDoc <span style='color:#111;'>527.50KB</span>","children":null,"spread":false},{"title":"[16]-PWR2V5,1V5.SchDocPreview <span style='color:#111;'>63.24KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1.PrjPcbStructure <span style='color:#111;'>6.79KB</span>","children":null,"spread":false},{"title":"[18]-POWERSEQUENCING.SchDocPreview <span style='color:#111;'>52.08KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1_PCB.html <span style='color:#111;'>18.14KB</span>","children":null,"spread":false},{"title":"[17]-MECH.SchDoc <span style='color:#111;'>37.50KB</span>","children":null,"spread":false},{"title":"[18]-POWERSEQUENCING.SchDoc <span style='color:#111;'>22.50KB</span>","children":null,"spread":false},{"title":"[16]-PWR2V5,1V5.SchDoc <span style='color:#111;'>413.00KB</span>","children":null,"spread":false},{"title":"[11]-CPU-POWER.SchDocPreview <span style='color:#111;'>121.41KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1_PCB.PcbLib <span style='color:#111;'>0B</span>","children":null,"spread":false},{"title":"iMX6RexJobFile.OutJob <span style='color:#111;'>49.72KB</span>","children":null,"spread":false},{"title":"[12]-CPU-UNUSED.SchDocPreview <span style='color:#111;'>126.57KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1.Annotation <span style='color:#111;'>0B</span>","children":null,"spread":false},{"title":"[09]-CPU-UART,AUDIO.SchDocPreview <span style='color:#111;'>67.00KB</span>","children":null,"spread":false},{"title":"[10]-CPU-JTAG,CONTROL.SchDoc <span style='color:#111;'>685.00KB</span>","children":null,"spread":false},{"title":"[11]-CPU-POWER.SchDoc <span style='color:#111;'>1.13MB</span>","children":null,"spread":false},{"title":"iMX6RexWorkspace.DsnWrk <span style='color:#111;'>75B</span>","children":null,"spread":false},{"title":"[12]-CPU-UNUSED.SchDoc <span style='color:#111;'>263.50KB</span>","children":null,"spread":false},{"title":"[15]-PWR3V3,1V375.SchDocPreview <span style='color:#111;'>82.89KB</span>","children":null,"spread":false},{"title":"[03]-CONNECTORS.SchDocPreview <span style='color:#111;'>79.81KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1Project.Dat <span style='color:#111;'>2.11KB</span>","children":null,"spread":false},{"title":"[08]-CPU-SPI,I2C,SD,MMC.SchDocPreview <span style='color:#111;'>107.63KB</span>","children":null,"spread":false},{"title":"[15]-PWR3V3,1V375.SchDoc <span style='color:#111;'>559.50KB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1_PCB.PcbDoc <span style='color:#111;'>9.90MB</span>","children":null,"spread":false},{"title":"iMX6Rex_V1I1_PCB.drc <span style='color:#111;'>4.08KB</span>","children":null,"spread":false},{"title":"[07]-CPU-USB,ETHERNET.SchDocPreview <span style='color:#111;'>80.01KB</span>","children":null,"spread":false},{"title":"[01]-COVERPAGE.SchDoc <span style='color:#111;'>27.50KB</span>","children":null,"spread":false},{"title":"[10]-CPU-JTAG,CONTROL.SchDocPreview <span style='color:#111;'>104.80KB</span>","children":null,"spread":false},{"title":"read_me.txt <span style='color:#111;'>104B</span>","children":null,"spread":false}],"spread":false},{"title":"iMX6RexModule_V1I1-2013bom.xlsx <span style='color:#111;'>35.56KB</span>","children":null,"spread":false}],"spread":true}],"spread":true}]